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1.发明授权公开(公告)号：US07515469B1
公开(公告)日：2009-04-07
申请号：US11862436
申请日：2007-09-27
CPC分类号： G11C29/848 , G11C16/04 , G11C29/789 , G11C2229/726
摘要： A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
摘要翻译： 用于非易失性存储器的列冗余系统包括单独的伴随控制器芯片，其包括用于存储有缺陷的非易失性存储器单元的地址的列冗余RAM存储器阵列。 列冗余匹配逻辑提供对应于非易失性存储器的特定用户输入地址与有缺陷的非易失性存储器单元的地址的匹配的匹配输出信号，存储在列冗余RAM存储器阵列中的所述地址的收集 。 列冗余替换逻辑响应于匹配输出，动态地将与有缺陷的非易失性存储器单元相关联的正确数据替换为非易失性存储器芯片的I / O程序或读取数据位流。
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公开(公告)号：US20090086541A1
公开(公告)日：2009-04-02
申请号：US11862436
申请日：2007-09-27
IPC分类号： G11C16/06
CPC分类号： G11C29/848 , G11C16/04 , G11C29/789 , G11C2229/726
摘要： A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.
摘要翻译： 用于非易失性存储器的列冗余系统包括单独的伴随控制器芯片，其包括用于存储有缺陷的非易失性存储器单元的地址的列冗余RAM存储器阵列。 列冗余匹配逻辑提供对应于非易失性存储器的特定用户输入地址与有缺陷的非易失性存储器单元的地址的匹配的匹配输出信号，存储在列冗余RAM存储器阵列中的所述地址的收集 。 列冗余替换逻辑响应于匹配输出，动态地将与有缺陷的非易失性存储器单元相关联的正确数据替换为非易失性存储器芯片的I / O程序或读取数据位流。
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公开(公告)号：US09037890B2
公开(公告)日：2015-05-19
申请号：US13559320
申请日：2012-07-26
申请人： Richard V De Caro , Danut Manea , Yongliang Wang , Stephen Trinh , Paul Hill
发明人： Richard V De Caro , Danut Manea , Yongliang Wang , Stephen Trinh , Paul Hill
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/3275 , G06F1/3287 , G11C5/147 , G11C5/148 , G11C16/30 , G11C2216/30 , Y02D10/14 , Y02D50/20
摘要： A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
摘要翻译： 存储器件包括电压调节器，其输出为存储器件的各种其他部件提供电压供应，包括命令用户界面。 存储器件通过向存储器件提供软件命令而被置于超深度掉电模式，该命令导致电压调节器的输出被禁止。 为了使存储器件脱离超深度掉电模式，芯片选择信号被提供给存储器件，其包括即使当存储器件处于超深度功率时仍保持通电的唤醒电路 降模式。 当存储器件处于超深度掉电模式时，芯片选择信号的接收使得电压调节器的输出被使能，从而为完全断电的部件提供电力。
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公开(公告)号：US20130250692A1
公开(公告)日：2013-09-26
申请号：US13425203
申请日：2012-03-20
申请人： Danut Manea , Erwin Castillon , Uday Mudumba , Sabina Centazzo , Stephen Trinh , Dixie Nguyen
发明人： Danut Manea , Erwin Castillon , Uday Mudumba , Sabina Centazzo , Stephen Trinh , Dixie Nguyen
IPC分类号： G11C16/10
CPC分类号： G11C16/10
摘要： Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.
摘要翻译： 描述用于在非易失性存储器上执行写入操作的系统和技术。 所描述的系统包括存储器结构，其包括布置在字线和位线上的非易失性存储器单元和与存储器结构通信耦合的微控制器。 存储器结构可以包括布置在字线和位线上的非易失性存储器单元。 微控制器可以配置为接收数据写入存储器结构，使用字线的选定字线将数据写入存储器结构，检测到失败写入数据，应用于故障，负偏差 电压到负偏压周期期间的字线的一个或多个未选字线，并且在负偏压周期期间使用所选择的字线将数据写入存储器单元的部分。
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公开(公告)号：US20070025160A1
公开(公告)日：2007-02-01
申请号：US11190722
申请日：2005-07-27
申请人： Stephen Trinh
发明人： Stephen Trinh
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , H01L29/7883
摘要： A post-erase channel clearing procedure for double well, floating gate, non-volatile memory cells. The channel is cleared of charged particles coming from the floating gate after an erase operation in two steps. In the first step the charged particles are pushed into an upper substrate well below the floating gate but not allowed into a deeper well of opposite conductivity type relative to the upper well. After a brief time, T, the charged particles are pushed by a bias voltage into the deeper well from the upper well. This two step clearing procedure avoids device latchup that might occur otherwise.
摘要翻译： 用于双阱，浮动栅极，非易失性存储单元的擦除后通道清除程序。 在擦除操作两个步骤之后，通道将清除来自浮动栅极的带电粒子。 在第一步骤中，带电粒子被压入浮动栅极下方的上基板中，但不允许进入相对于上阱的相反导电类型的较深阱。 在短暂的时间之后，T，带电粒子被偏置电压推到较深的井中。 这两步清除过程可以避免可能会发生的设备闭锁。
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公开(公告)号：US20140032956A1
公开(公告)日：2014-01-30
申请号：US13559320
申请日：2012-07-26
申请人： Richard V. De Caro , Danut Manea , YONGLIANG WANG , Stephen Trinh , Paul Hill
发明人： Richard V. De Caro , Danut Manea , YONGLIANG WANG , Stephen Trinh , Paul Hill
IPC分类号： G06F1/32
CPC分类号： G06F1/3296 , G06F1/26 , G06F1/3203 , G06F1/3206 , G06F1/3275 , G06F1/3287 , G11C5/147 , G11C5/148 , G11C16/30 , G11C2216/30 , Y02D10/14 , Y02D50/20
摘要： A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.
摘要翻译： 存储器件包括电压调节器，其输出为存储器件的各种其他部件提供电压供应，包括命令用户界面。 存储器件通过向存储器件提供软件命令而被置于超深度掉电模式，该命令导致电压调节器的输出被禁止。 为了使存储器件脱离超深度掉电模式，芯片选择信号被提供给存储器件，其包括即使当存储器件处于超深度功率时仍保持通电的唤醒电路 降模式。 当存储器件处于超深度掉电模式时，芯片选择信号的接收使得电压调节器的输出被使能，从而为完全断电的部件提供电力。
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公开(公告)号：US20070097760A1
公开(公告)日：2007-05-03
申请号：US11266501
申请日：2005-11-03
申请人： Stephen Trinh , Dixie Nguyen
发明人： Stephen Trinh , Dixie Nguyen
IPC分类号： G11C29/00
摘要： A memory system incorporating redundancy utilizes a content addressable memory to monitor addresses during memory accesses. The content addressable memory provides a pointer to an alternate memory location when a previously determined faulty location is requested. Redundant memory cells are accessed by use of column redundancy information output from the content addressable memory. During a memory access cycle a register in the content addressable memory latches a memory address. The content addressable memory decodes the address and produces column redundancy information as an output. The column redundancy information is latched during a period complementary to the memory access cycle. By utilizing complementary memory access phases to latch memory addresses in contrast with a utilization of column redundancy information, a single set of registers may be used. Additionally, concurrent read and write operations are supported.
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公开(公告)号：US08885413B2
公开(公告)日：2014-11-11
申请号：US13425203
申请日：2012-03-20
申请人： Danut Manea , Erwin Castillon , Uday Mudumba , Sabina Centazzo , Stephen Trinh , Dixie Nguyen
发明人： Danut Manea , Erwin Castillon , Uday Mudumba , Sabina Centazzo , Stephen Trinh , Dixie Nguyen
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period.
摘要翻译： 描述用于在非易失性存储器上执行写入操作的系统和技术。 所描述的系统包括存储器结构，其包括布置在字线和位线上的非易失性存储器单元和与存储器结构通信耦合的微控制器。 存储器结构可以包括布置在字线和位线上的非易失性存储器单元。 微控制器可以配置为接收数据写入存储器结构，使用字线的选定字线将数据写入存储器结构，检测到写入数据失败，应用于故障，负偏差 电压到负偏压周期期间的字线的一个或多个未选字线，并且在负偏压周期期间使用所选择的字线将数据写入存储器单元的部分。
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