公开(公告)号：US6094395A

公开(公告)日：2000-07-25

申请号：US253996

申请日：1999-02-22

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C7/00

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/147

摘要： A plurality of voltage generating circuits forming a voltage generator system on a chip are controlled by a centralized voltage generator control arrangement. The voltage generator control arrangement includes a controller with a state machine (52) that receives control signals from various devices on the chip as, for example, a clock generator, voltage detectors, bondpads, testpads, fuses, and predetermined registers. From the received signals, the controller generates control signals to the plurality of generating circuits of the voltage generator system and other circuits on the chip in accordance with a predetermined program sequence for each phase of operation required by the generating circuits to provide the necessary stable voltages to circuits on the chip.

摘要翻译： 在芯片上形成电压发生器系统的多个电压产生电路由集中式电压发生器控制装置控制。 电压发生器控制装置包括具有状态机（52）的控制器，该状态机从芯片上的各种装置接收控制信号，例如时钟发生器，电压检测器，键盘，测试板，保险丝和预定寄存器。 根据接收到的信号，控制器根据预定的程序序列产生电压发生器系统的多个发生电路和芯片上的其它电路的控制信号，以产生电路所要求的每个运行阶段提供必要的稳定电压 到芯片上的电路。

公开(公告)号：US5959471A

公开(公告)日：1999-09-28

申请号：US937571

申请日：1997-09-25

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： G11C11/407 ,  G05F1/46 ,  G05F1/56 ,  H01L21/822 ,  H01L27/04 ,  H03K5/153

CPC分类号： G05F1/462

摘要： A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

摘要翻译： 提供了一种用于在同步DRAM处于备用断电模式的同时降低参考电压电路的电流消耗的方法。 参考电压存储在DRAM电路内的电容器上。 为了确保泄漏补偿，参考电压电路在断电模式期间以预定的时间间隔选择性地断开和重新连接到Vref节点。 当掉电模式超过预定时间时，禁止参考电压电路进一步降低电流消耗。

公开(公告)号：US5933374A

公开(公告)日：1999-08-03

申请号：US97545

申请日：1998-06-15

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： G11C29/06 ,  G11C5/06 ,  G11C5/14 ,  G11C19/00 ,  G11C16/04

CPC分类号： G11C5/143 ,  G11C5/066 ,  G11C5/147

摘要： In memory systems embodying the invention a controller/sequencer circuit converts a multiplicity of control signals into a serial stream of control signals which are carried from the controller/sequencer circuit via a single ("data") line to the data input of a control path (e.g., a multi-stage shift register) which is disposed in proximity to a functions generator (e.g., a voltages generator). After the control path is serially loaded with a selected number of control signals, the control signals are selectively applied, in parallel, to the functions generator. Where the control path is a shift register, three control lines are routed from the controller/sequencer to the shift register. One line carries the serial control signals to the input of the shift register; one line (i.e., a shift line) carries shift signals for causing the transfer of the control signals along the shift register stages; and one line (i.e., a select line) is used to selectively transfer control signals accumulated in the shift register to the voltages generator.

摘要翻译： 在体现本发明的存储器系统中，控制器/定序器电路将多个控制信号转换成从控制器/定序器电路经由单个（“数据”）线传送到控制路径的数据输入的串行控制信号流 （例如，多级移位寄存器），其布置在功能发生器（例如，电压发生器）附近。 在控制路径以选定数量的控制信号串行加载之后，控制信号被并行地选择性地施加到功能发生器。 在控制路径是移位寄存器的情况下，三个控制线从控制器/定序器发送到移位寄存器。 一行将串行控制信号传送到移位寄存器的输入端; 一行（即移位线）携带用于使控制信号沿着移位寄存器级的传送的移位信号; 并且使用一行（即，选择线）来选择性地将累积在移位寄存器中的控制信号传送到电压发生器。

公开(公告)号：US06530051B1

公开(公告)日：2003-03-04

申请号：US09534102

申请日：2000-03-23

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： G11C800

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074

摘要： In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of N states. A state storage device is responsive to input signals from a transition arrangement including a 1-out-of-N code indicating a change in the state diagram from a current state to a next state of the plurality of N states. The state storage device generates a revised plurality of N state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of N states. The state storage device is also responsive to an asynchronous Reset signal received from an external source for generating a Reset and a complementary Set output signal. A state identification circuitry is responsive to a selectively applied activation signal for inhibiting the output of the revised plurality of N state signals from the state storage device and sequentially reading out the plurality of N state signals currently stored in the state storage device. The the 1-out-of N-code forming the plurality of N state signals are used to determine which state of the state diagram the controller is presently in when the controller fails to complete a procedure in the state diagram.

摘要翻译： 在用于控制存储器芯片上的发电机系统的控制器中，控制器根据包括多个N状态的状态图作为状态机操作。 状态存储装置响应来自包括指示状态图从当前状态到多个N状态的下一状态的1-out-N代码的转换装置的输入信号。 状态存储装置产生修正的多个N状态输出信号，其包括用于多个N状态的下一状态的真实状态信号和补充真实状态信号。 状态存储装置还响应于从外部源接收的用于产生复位和互补设置输出信号的异步复位信号。 状态识别电路响应于选择性地施加的激活信号，用于禁止来自状态存储装置的经修订的多个N状态信号的输出，并且顺序读出当前存储在状态存储装置中的多个N状态信号。 形成多个N状态信号的1输出N代码用于确定当控制器在状态图中未完成过程时控制器当前处于的状态图的状态。

公开(公告)号：US06483764B2

公开(公告)日：2002-11-19

申请号：US09761045

申请日：2001-01-16

申请人： Louis Lu Chen Hsu ,  Gerd Frankowsky ,  Oliver Weinfurtner

发明人： Louis Lu Chen Hsu ,  Gerd Frankowsky ,  Oliver Weinfurtner

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C2207/104 ,  G11C2207/2254

摘要： A novel DRAM refresh method and system and a novel method of designing a low-power leakage monitoring device. With the DRAM refresh method, the time is adjusted based directly on the cell leakage condition. The method of designing a low-power leakage monitoring devices uses a memory cell identical to the cells in the real array. This monitor cell is designed so that it will represent the average cell or the worst cell leakage condition. If the leakage is severe, the refresh cycle time is significantly reduced, or halved. If the leakage level is very low or undetectable, then the refresh cycle time is significantly increased, or doubled. If the leakage is moderate, or in the normal range, the refresh time is optimized, so that the power consumption used for DRAM refresh is minimized. The advantages of this method over the existing method, that is, adjusting the refresh cycle time based on chip temperature include (1) the contributions from non-temperature dependent leakage factors are taken into consideration, (2) the present invention does not require different process steps, or extra process costs to integrate such device in the chip, and (3) the present invention is a straight forward method, the monitor cell does not need any calibration. In addition, its leakage mechanism and reliability concern are all identical to the cells in a real array.

摘要翻译： 一种新颖的DRAM刷新方法和系统以及设计低功耗漏电监测装置的新方法。 利用DRAM刷新方法，基于单元泄漏状况来调整时间。 设计低功率泄漏监测装置的方法使用与真实阵列中的单元相同的存储单元。 该监视器单元被设计成它将代表平均单元或最坏的单元泄漏状况。 如果泄漏严重，则刷新周期时间会显着减少或减半。 如果泄漏电平非常低或不可检测，则刷新周期时间显着增加或加倍。 如果泄漏中等或在正常范围内，则刷新时间被优化，使得用于DRAM刷新的功耗最小化。 该方法优于现有方法，即基于芯片温度调整刷新周期时间的优点包括：（1）考虑到非温度依赖性泄漏因素的贡献，（2）本发明不需要不同的 处理步骤或额外的处理成本，以及（3）本发明是一种直接的方法，监测单元不需要任何校准。 此外，其泄漏机制和可靠性问题与实际阵列中的单元格完全相同。

公开(公告)号：US06275096B1

公开(公告)日：2001-08-14

申请号：US09460820

申请日：1999-12-14

申请人： Louis L. C. Hsu ,  Oliver Weinfurtner ,  Matthew R. Wordeman

发明人： Louis L. C. Hsu ,  Oliver Weinfurtner ,  Matthew R. Wordeman

IPC分类号： G05F302

CPC分类号： H02M3/07

摘要： A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

摘要翻译： 提供一种电荷泵发电机系统和方法，其通过根据电压源达到的电压水平操作一些或全部可用电荷泵，从而更精确地保持内部产生的电压源的电平。 当电源远离其目标电平时，第一组和第二组电荷泵被操作。 第一组可优选具有比第二组更快的泵送速率或更大数量的电荷泵。 当电压提供超过第一预定电平时，第一组电荷泵关闭，而第二组保持接通，使得电荷转移速率变慢。 第二组继续运行直到第二组，例如， 目标，超过电压电平。 然后，较慢的电荷转移速率有效地减少了耦合到电源线上的过冲，振铃和噪声。 优选地，至少一个电荷泵在备用和有源模式下工作，从而减少芯片面积。

公开(公告)号：US06269049B1

公开(公告)日：2001-07-31

申请号：US09533526

申请日：2000-03-23

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： G11C800

CPC分类号： G11C5/147

摘要： In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system while providing substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.

摘要翻译： 在用于控制存储器芯片上的发电机系统的控制器中，控制器根据包括多个X状态的状态图作为状态机操作。 状态存储装置响应于指示状态图从当前状态到下一状态的变化的输入信号，用于产生修正的多个X状态输出信号，该X状态输出信号包括用于下一状态的真实状态信号和补充真状态信号 多个X状态。 输出装置响应来自状态存储装置的经修正的多个X状态输出信号中的真实状态信号和补充真实状态信号，用于产生与用于控制发电机系统的所述下一个状态相关联的M个输出信号的单独的预定的一个， 当状态图达到多个X状态的最终状态时，提供基本上为零的电流消耗。

公开(公告)号：US6044163A

公开(公告)日：2000-03-28

申请号：US864066

申请日：1997-05-28

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： H04R25/00

CPC分类号： H04R25/507

摘要： A hearing aid has an input transducer, an amplifier and transmission circuit, an output transducer and a calculating unit working according to the principle of a neural structure. The calculating unit responds to a tap signal taken at the amplifier and transmission circuit and units an event signal that is supplied to the amplifier and transmission circuit and influences an output signal emitted thereby. At least the calculating unit is implemented in digital circuit technology. Such a hearing aid can be manufactured with little development and circuit outlay, works reliably and enables an optimum matching to the specific requirements of the hearing aid user.

摘要翻译： 助听器具有根据神经结构原理工作的输入换能器，放大器和传输电路，输出换能器和计算单元。 计算单元响应于在放大器和传输电路处采集的抽头信号，并且单元提供提供给放大器和传输电路的事件信号，并影响由此发射的输出信号。 至少在数字电路技术中实现了计算单元。 这样的助听器可以以很少的开发和电路支出制造，可靠地工作，并且能够对助听器用户的特定要求进行最佳匹配。

公开(公告)号：US5717770A

公开(公告)日：1998-02-10

申请号：US393819

申请日：1995-02-24

申请人： Oliver Weinfurtner

发明人： Oliver Weinfurtner

IPC分类号： H03G3/00 ,  H03G3/20 ,  H04R25/00

CPC分类号： H04R25/507 ,  H03G3/001 ,  H03G3/3026 ,  Y10S706/90

摘要： A hearing aid with a simplified and optimized control system has control functions that are entirely or partially implemented by a fuzzy logic controller in the amplifier and transmission part circuitry.

摘要翻译： 具有简化和优化的控制系统的助听器具有由放大器和传输部分电路中的模糊逻辑控制器完全或部分实现的控制功能。

公开(公告)号：US06285619B1

公开(公告)日：2001-09-04

申请号：US09442982

申请日：1999-11-18

申请人： Gabriel Daniel ,  Oliver Weinfurtner

发明人： Gabriel Daniel ,  Oliver Weinfurtner

IPC分类号： G11C700

CPC分类号： G11C17/16 ,  G11C17/14

摘要： A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

摘要翻译： 提供了一种用于存储数据位的电路，其中电路包括具有第一端和第二端的第一保险丝和具有第三端和第四端的第二保险丝。 第一个保险丝的第一端连接到一个逻辑0输入，其第二端连接到一个公共输出端。 第二个保险丝的第三端连接到逻辑1输入，第四端连接到公共输出端。 为了存储数据位，选择性地吹制第一和第二熔丝之一。 因此，可以使用两个保险丝来存储一些信息。