公开(公告)号：US6127874A

公开(公告)日：2000-10-03

申请号：US939443

申请日：1997-09-29

申请人： Shigemichi Wakabayashi ,  Toshiyuki Oshima ,  Osamu Fuji ,  Shoichi Miyamoto

发明人： Shigemichi Wakabayashi ,  Toshiyuki Oshima ,  Osamu Fuji ,  Shoichi Miyamoto

IPC分类号： H01L21/822 ,  G06F1/10 ,  G06F17/50 ,  H01L21/82 ,  H01L27/04 ,  H03K19/096 ,  H03K19/173 ,  H03K3/013

CPC分类号： G06F1/10 ,  G06F17/5045

摘要： The present invention provides a semiconductor IC and a method for designing the same which adjusts the clock skews on a chip without additional delay circuit. A decrease in design time is realized when the semiconductor IC includes hard megacells (whose functions have been confirmed) or standard cell blocks. In the case of a semiconductor IC including hard megacells and a standard cell blocks, each megacell and standard cell block according to the present invention has sub-clock buffers on every row, for example, sub-clock buffers on the row and sub-clock buffers on the row in the megacell. The adjustment needed for accommodating clock skews on a chip is determined by calculating a delay time for the various IC chip blocks. Next, sub-clock buffers are chosen based on a result of a calculation for the delay time. Finally, the wiring design is completed which minimizes clock skew.

摘要翻译： 本发明提供一种半导体IC及其设计方法，用于调整芯片上的时钟偏差而不需要额外的延迟电路。 当半导体IC包括硬兆字节（其功能已被确认）或标准单元块时，实现了设计时间的减少。 在包括硬兆赫和标准单元块的半导体IC的情况下，根据本发明的每个兆位和标准单元块在每行上具有子时钟缓冲器，例如行和子时钟上的子时钟缓冲器 在megacell行上的缓冲区。 通过计算各种IC芯片块的延迟时间来确定在芯片上适应时钟偏移所需的调整。 接下来，基于延迟时间的计算结果来选择子时钟缓冲器。 最后，完成了布线设计，使时钟偏移最小化。