公开(公告)号：US20070091669A1

公开(公告)日：2007-04-26

申请号：US11257327

申请日：2005-10-24

申请人： Owen Hynes ,  Roy Wang ,  Romney Katti ,  Daniel Reed

发明人： Owen Hynes ,  Roy Wang ,  Romney Katti ,  Daniel Reed

IPC分类号： G11C11/00

CPC分类号： G11C11/15

摘要： A magneto-resistive memory system is presented that includes a radiation-hardened and low power memory cell. The magneto-resistive memory cell includes a word line select transistor in the cell to help eliminate unselected cell disturbances. Furthermore, the magneto-resistive memory cell includes a full-turn write word line that writes true and complimentary bit values using less current than previous cell architectures. The improved memory cell may be used in a memory system with precision current drivers and auto-zero sense amplifiers in order to further lower power and improve overall system reliability.

摘要翻译： 提出了一种包含辐射硬化和低功率存储单元的磁阻存储器系统。 磁阻存储单元包括单元中的字线选择晶体管，以帮助消除未选择的单元干扰。 此外，磁阻存储器单元包括使用比以前的单元架构更少的电流写入真实和互补位值的全匝写入字线。 改进的存储单元可以用于具有精密电流驱动器和自动零感测放大器的存储器系统中，以便进一步降低功率并提高整体系统的可靠性。

公开(公告)号：US20070023840A1

公开(公告)日：2007-02-01

申请号：US11185262

申请日：2005-07-20

申请人： Owen Hynes

发明人： Owen Hynes

IPC分类号： H01L23/62

CPC分类号： H01L27/0285

摘要： A novel system for protecting one or more circuits during a dose rate event is presented. A clamping circuit is utilized that outputs a voltage signal that may be used to control prevent circuits from receiving input signals during a dose rate event. The clamping circuit comprises a photocurrent generating device that creates a current as a function of dose rate event strength. This current is used to control a grounding switch, which pulls the clamping circuit output to ground when a substantial current is created by the photocurrent generating device. The clamping circuit output may control a coupling switch that permits external input signal current flow when the clamping circuit output is above a threshold voltage level, and may prevent current flow when the output is grounded. The photocurrent generating device may be a PMOS device, while the coupling switch and clamping switch may be realized by NMOS devices.

摘要翻译： 提出了一种用于在剂量率事件期间保护一个或多个电路的新型系统。 使用钳位电路，其输出可用于控制阻止电路在剂量率事件期间接收输入信号的电压信号。 钳位电路包括光电流产生装置，其产生作为剂量率事件强度的函数的电流。 该电流用于控制接地开关，当由光电流产生装置产生大量电流时，该接地开关将钳位电路输出接地。 钳位电路输出可以控制耦合开关，当钳位电路输出高于阈值电压电平时，允许外部输入信号电流流动，并且可以在输出接地时防止电流流动。 光电流产生装置可以是PMOS器件，而耦合开关和钳位开关可以由NMOS器件实现。

公开(公告)号：US20060221675A1

公开(公告)日：2006-10-05

申请号：US11096179

申请日：2005-03-31

申请人： Owen Hynes ,  Romney Katti ,  Harry Liu ,  Michael Liu

发明人： Owen Hynes ,  Romney Katti ,  Harry Liu ,  Michael Liu

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A system and method for protecting MRAM bits during a dose rate event is described. A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be used to protect an entire row and/or column of MRAM bits.

摘要翻译： 描述了在剂量率事件期间保护MRAM位的系统和方法。 器件与MRAM位的MTJ结构并联连接，以在剂量率事件期间跨越MTJ结构分流光电流和/或限制跨越MTJ结构的电压。 该器件可以包括至少一个晶体管和/或至少一个二极管。 一个设备可用于保护MRAM位的整个行和/或列。

公开(公告)号：US09136217B2

公开(公告)日：2015-09-15

申请号：US13608595

申请日：2012-09-10

申请人： Jonathan Schmitt ,  Roy Milton Carlson ,  Yong Lu ,  Owen Hynes

发明人： Jonathan Schmitt ,  Roy Milton Carlson ,  Yong Lu ,  Owen Hynes

IPC分类号： G11C17/00 ,  H01L23/525 ,  H01L27/06 ,  H01L27/10

CPC分类号： H01L23/5252 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.

摘要翻译： 包括厚氧化物间隔晶体管，与厚氧化物隔离晶体管相邻设置的可编程薄氧化物反熔丝以及第一和第二厚氧化物存取晶体管的可编程存储单元。 厚氧化物间隔晶体管和第一和第二厚氧化物存取晶体管可以包括比可编程薄氧化物反熔丝的氧化物层厚的氧化物层。 可编程薄氧化物反熔丝和厚氧化物间隔晶体管可以是本征掺杂的。 可以掺杂第一和第二厚氧化物存取晶体管以具有标准阈值电压特性。

公开(公告)号：US20070109839A1

公开(公告)日：2007-05-17

申请号：US11273214

申请日：2005-11-14

申请人： Romney Katti ,  Owen Hynes ,  Daniel Reed ,  Hassan Kaakani

发明人： Romney Katti ,  Owen Hynes ,  Daniel Reed ,  Hassan Kaakani

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A new read scheme is provided for an MRAM bit having a pinned layer (fixed) and a storage layer (free) sandwiching a nonmagnetic spacer layer. By applying a magnetic field to the bit at least partially orthogonal to the easy axis of the bit, the magnetization direction of the storage layer can be partially rotated or canted without switching the logical state of the MRAM bit. The resistivity of the bit is measured (calculated based on a voltage/current relationship) in two ways: (i) with the magnetization direction of the storage layer partially rotated in a first direction and (ii) with the magnetization direction of the storage layer in its bi-stable orientation parallel to the easy axis. Those measures can then be used to compare and determine the logical state of the storage layer. For instance, if the canted resistivity is greater than the uncanted resistivity then the magnetization directions of the pinned and storage layer are parallel, and if the canted resistivity is less than the uncanted resistivity then the magnetization directions of the pinned and storage layer are opposite.

摘要翻译： 为具有钉扎层（固定）和夹持非磁性间隔层的存储层（自由）的MRAM位提供了新的读取方案。 通过将至少部分地正交于该位的容易轴的位施加磁场，可以在不切换MRAM位的逻辑状态的情况下部分地旋转或倾斜存储层的磁化方向。 以两种方式测量位的电阻率（基于电压/电流关系计算）：（i）存储层的磁化方向在第一方向上部分旋转，并且（ii）与存储层的磁化方向 其平行于易轴的双稳态取向。 然后可以使用这些措施来比较和确定存储层的逻辑状态。 例如，如果倾斜电阻率大于无电阻率，那么被钉扎层和存储层的磁化方向是平行的，并且如果斜面电阻率小于未被覆盖的电阻率，那么被钉扎和存储层的磁化方向相反。

公开(公告)号：US20140071731A1

公开(公告)日：2014-03-13

申请号：US13608595

申请日：2012-09-10

申请人： Jonathan Schmitt ,  Roy Milton Carlson ,  Yong Lu ,  Owen Hynes

发明人： Jonathan Schmitt ,  Roy Milton Carlson ,  Yong Lu ,  Owen Hynes

IPC分类号： G11C17/12 ,  H01L27/088

CPC分类号： H01L23/5252 ,  H01L27/0629 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable memory cell including a thick oxide spacer transistor, a programmable thin oxide anti-fuse disposed adjacent to the thick oxide spacer transistor, and first and second thick oxide access transistors. The thick oxide spacer transistor and first and second thick oxide access transistors can include an oxide layer that is thicker than an oxide layer of the programmable thin oxide anti-fuse. The programmable thin oxide anti-fuse and the thick oxide spacer transistor can be natively doped. The first and second thick oxide access transistors can be doped so as to have standard threshold voltage characteristics.

摘要翻译： 包括厚氧化物间隔晶体管，与厚氧化物隔离晶体管相邻设置的可编程薄氧化物反熔丝以及第一和第二厚氧化物存取晶体管的可编程存储单元。 厚氧化物间隔晶体管和第一和第二厚氧化物存取晶体管可以包括比可编程薄氧化物反熔丝的氧化物层厚的氧化物层。 可编程薄氧化物反熔丝和厚氧化物间隔晶体管可以是本征掺杂的。 可以掺杂第一和第二厚氧化物存取晶体管以具有标准阈值电压特性。