-
公开(公告)号：US07151473B2
公开(公告)日：2006-12-19
申请号：US11203717
申请日：2005-08-15
IPC分类号： H03M1/84
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译： 提供接收器100。 接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅 模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益 来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比。 在一个实施例中，接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。 在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。
-
公开(公告)号：US06643499B1
公开(公告)日：2003-11-04
申请号：US09603741
申请日：2000-06-26
申请人： Pascal Audinot , Andrew M. Henwood
发明人： Pascal Audinot , Andrew M. Henwood
IPC分类号： H04B106
CPC分类号： H03C3/0983 , H03C3/0966 , H03L7/18 , H03L7/185
摘要： A first and second phase-locked loop each having their frequency of operation under programmable control by changing the divider ratio. A single programming word contains the divider ratio for the first phase-locked loop and addressing bits which address a plurality of auxiliary registers for changing the divider ratio of the second phase-locked loop. In a cellular telephone, this allows the digital signal processor to change from receive to transmit mode or from one transmit mode or from one frequency to another utilizing a single command word.
摘要翻译： 第一和第二锁相环，通过改变分频比，每个具有可编程控制的操作频率。 单个编程字包含第一锁相环的分频比和寻址多个辅助寄存器的寻址位，用于改变第二锁相环的分频比。 在蜂窝电话中，这允许数字信号处理器使用单个命令字从接收模式或发送模式或从一种频率改变到另一个。
-
3.发明授权公开(公告)号：US06947496B2
公开(公告)日：2005-09-20
申请号：US09962687
申请日：2001-09-25
摘要： A method for refining a DC-Offset estimate and removing of the DC-Offset includes the step of determining if any AM is present (602). If AM is determined to be present, it is next determined if the I and Q path DC-Offset estimates are closely matched, if they are, then only a single search using the average of the I and Q path estimates is used (608). If it determined however, that the two path estimates are not closely matched, than two searches are performed, one for each path (610). After this, the blocking signals are searched for up to a predetermined number and the DC-Offset vector is generated (612). Once the DC-Offset vector is generated, the DC-Offset is removed from the received signal (614). After which it is determined if the AM level is high (616), and if so, a transient correction routine is performed (618).
摘要翻译： 用于细化DC偏移估计和去除DC偏移的方法包括确定是否存在AM的步骤（602）。 如果确定AM存在，则接下来确定I和Q路径DC偏移估计是否紧密匹配，如果是，则仅使用使用I和Q路径估计的平均值的单个搜索（608） 。 然而，如果确定两个路径估计不紧密匹配，则执行两次搜索，每个路径一个（610）。 之后，搜索阻塞信号达预定数量，并产生DC偏移向量（612）。 一旦DC偏移矢量被产生，则DC-Offset从接收信号中去除（614）。 之后确定AM电平是否高（616），如果是，则执行瞬态校正程序（618）。
-
公开(公告)号：US20060055579A1
公开(公告)日：2006-03-16
申请号：US11203717
申请日：2005-08-15
IPC分类号： H03M1/12
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译： 提供接收器100。 接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅 模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益 来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比地成比例。在一个实施例中 接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。 在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。
-
公开(公告)号：US06947495B2
公开(公告)日：2005-09-20
申请号：US09962643
申请日：2001-09-25
CPC分类号： H04L25/061
摘要： A method for estimating and removing a time varying DC-offset includes the steps of dividing the received burst into blocks (902), then finding the maximum and minimum values in each block (904). Once the maximums and minimum values have been found, the upper and lower envelopes are determined (906). The DC-offset path is then calculated by taking the average of the upper and lower envelope (908). Once determined, the DC-offset path information is used in order to subtract the DC-offset from the desired signal.
摘要翻译： 用于估计和去除时变DC偏移的方法包括以下步骤：将接收的脉冲串划分为块（902），然后找到每个块中的最大值和最小值（904）。 一旦找到最大值和最小值，就确定上下包络（906）。 然后通过取上下包络线的平均值（908）来计算直流偏移路径。 一旦确定，则使用DC偏移路径信息以便从期望信号中减去DC偏移。
-
公开(公告)号：US07565125B2
公开(公告)日：2009-07-21
申请号：US10601348
申请日：2003-06-23
申请人： Pascal Audinot , Vincent Roussel
发明人： Pascal Audinot , Vincent Roussel
CPC分类号： H03G3/3052 , H03G3/3068 , H03M1/183
摘要： A receiver 30 has an adjustable gain control circuit 32 that provides gain control base on the magnitude of the signal at the input of an analog-to-digital converter 22. The magnitude of a gain increase or decrease can be based on the most significant bits of the analog-to-digital output, indicating whether the analog-to-digital converter is close to saturation, approaching saturation, or well below saturation.
摘要翻译： 接收器30具有可调节增益控制电路32，其基于模数转换器22的输入处的信号幅度提供增益控制。增益或减小的幅度可以基于最高有效位 的模拟数字输出，指示模数转换器是否接近饱和，接近饱和或远低于饱和。
-
公开(公告)号：US07466968B2
公开(公告)日：2008-12-16
申请号：US09962417
申请日：2001-09-25
申请人： Pascal Audinot
发明人： Pascal Audinot
CPC分类号： H04B1/406
摘要： A multi-band RF transceiver (100) includes a single dual band VCO (102) that is used in both transmit and receive modes of operation. The VCO's low band frequency output signal that is provided on output line (120) is multiplied by two by multiplier circuit (1302), when in the high band receive mode, as for example, when receiving a PCS or DCS signal. The VCO's high band frequency output signal provided on output line (120) is divided by two by divider circuit (130) when in the low band receive mode, as for example, when receiving a GSM signal. The single multi-band VCO (102) design provides for low susceptibility to both LO leakage and DC offset caused by radiation.
摘要翻译： 多频带RF收发器（100）包括用于发送和接收操作模式的单个双频带VCO（102）。 当处于高频带接收模式时，例如当接收到PCS或DCS信号时，通过乘法电路（1302）将输出线（120）上提供的VCO的低频带频率输出信号乘以2。 当处于低频带接收模式时，例如当接收到GSM信号时，由输出线（120）上提供的VCO的高频带频率输出信号由分频器电路（130）除以2。 单个多频带VCO（102）设计提供了对辐射引起的LO泄漏和DC偏移的低敏感性。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.01 秒)
