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公开(公告)号：US09473161B1
公开(公告)日：2016-10-18
申请号：US14849021
申请日：2015-09-09
发明人： Lynn Kern
摘要： A combination of a precision analog-to-digital converter (ADC), an analog amplifier having selectable gains and an intelligent controller to coordinate the amplifier gain selection and placement of the digital conversion results into at least one register provide for a very high resolution analog-to-digital conversion process, at a high sample rate and low power consumption. For example, a 14-bit ADC may be used with selectable gain analog amplification, e.g., ×1, ×2, ×4 and ×8, between the sampled signal and ADC input and an intelligent controller to provide a 17-bit conversion number having proper scaling of the digital sample words. The entire high resolution analog-to-digital conversion process may be automatically performed without additional control from external hardware/software.
摘要翻译： 精密模数转换器（ADC），具有可选择增益的模拟放大器和智能控制器的组合，用于协调放大器增益选择和将数字转换结果放置到至少一个寄存器中，提供非常高分辨率的模拟 数字转换过程，采样率高，功耗低。 例如，14位ADC可以采用可选增益模拟放大，例如采样信号和ADC输入之间的×1，×2，×4和×8，智能控制器提供17位转换数 具有适当缩放的数字样本单词。 可以自动执行整个高分辨率模数转换过程，而无需外部硬件/软件的附加控制。
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公开(公告)号：US20130259242A1
公开(公告)日：2013-10-03
申请号：US13798846
申请日：2013-03-13
申请人： NXP B.V.
IPC分类号： H04R3/00
摘要： A microphone circuit has a clip detection circuit which detects when an analogue to digital converter output has reached a threshold. A variable attenuator is controlled based on the clip detection circuit output. The feedback is thus based on the ADC output level, and the processing of this signal can be implemented without requiring baseband processing of the signal—it can simply be based on a state of the ADC output. An overrule function is also provided so that the clip detection AGC control can be inhibited or controlled differently.
摘要翻译： 麦克风电路具有检测模拟数字转换器输出何时达到阈值的片段检测电路。 可变衰减器基于片段检测电路输出进行控制。 因此，反馈基于ADC输出电平，并且可以实现该信号的处理而不需要信号的基带处理 - 它可以简单地基于ADC输出的状态。 还提供了一个推翻功能，使得可以不同地抑制或控制剪辑检测AGC控制。
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公开(公告)号：US08493256B2
公开(公告)日：2013-07-23
申请号：US13242719
申请日：2011-09-23
申请人： Niels Ole Knudsen
发明人： Niels Ole Knudsen
摘要： In order to minimize noise and current consumption in a hearing aid, an input converter comprising a first voltage transformer and an analog-to-digital converter of the delta-sigma type for a hearing aid is devised. The analog-to-digital converter of the input converter has an input stage, an output stage, and a feedback loop, and the input stage comprises an amplifier (QA) and an integrator (RLF). The first voltage transformer (IT) has a transformation ratio such that it provides an output voltage larger than the input voltage and is placed in the input converter upstream of the input stage. A second voltage transformer (OT) having a transformation ratio such that it provides an output voltage larger than the input voltage, is optionally placed in the feedback loop of the converter. The voltage transformers (IT, OT) are switched-capacitor voltage transformers, each transformer (IT, OT) having at least two capacitors (Ca, Cb, Cc, Cd). The invention further provides a method of converting an analog signal.
摘要翻译： 为了最小化助听器中的噪声和电流消耗，设计了一种包括第一电压互感器和用于助听器的delta-sigma类型的模 - 数转换器的输入转换器。 输入转换器的模数转换器具有输入级，输出级和反馈回路，输入级包括放大器（QA）和积分器（RLF）。 第一变压器（IT）具有变压比，使得它提供大于输入电压的输出电压，并被放置在输入转换器的上游输入级。 具有变压比使得其提供大于输入电压的输出电压的第二变压器（OT）可选地放置在转换器的反馈环路中。 电压互感器（IT，OT）是开关电容器电压互感器，每个变压器（IT，OT）具有至少两个电容器（Ca，Cb，Cc，Cd）。 本发明还提供一种转换模拟信号的方法。
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公开(公告)号：US20100156635A1
公开(公告)日：2010-06-24
申请号：US12714449
申请日：2010-02-27
IPC分类号： G08B21/00
CPC分类号： H03G3/001 , G01R19/04 , G01R19/2506 , H03G3/3042 , H03K5/1532 , H03M3/43 , H03M3/456 , H03M3/486 , H03M3/49
摘要： An electronic signal level detection system and method are provided. The method receives an analog input signal having a variable voltage and compares the input signal voltage to a threshold. A detection signal is generated for input signal voltages exceeding the threshold in a periodic first time frame. In a second periodic time frame (following the first time frame), a count is updated in response to the generated detection signals. The count is used to create a metric representative of the difference between the input signal voltage and the threshold. The count is incremented in response to the generating a detection signal (“1”) in the first time frame, and decremented in response to not generating a detection signal (“0”) in the first time frame.
摘要翻译： 提供电子信号电平检测系统和方法。 该方法接收具有可变电压的模拟输入信号，并将输入信号电压与阈值进行比较。 在周期性第一时间帧中，对超过阈值的输入信号电压产生检测信号。 在第二周期时间帧（在第一时间帧之后），响应于所生成的检测信号来更新计数。 该计数用于创建表示输入信号电压和阈值之间的差异的度量。 响应于在第一时间帧中产生检测信号（“1”），计数增加，并且响应于在第一时间帧中不产生检测信号（“0”）而递减计数。
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5.发明授权Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling 有权具有输入信号和共模电流归零的离散时间可编程增益模数转换器（ADC）输入电路公开(公告)号：US07492296B1
公开(公告)日：2009-02-17
申请号：US11864884
申请日：2007-09-28
IPC分类号： H03M1/00
摘要： A discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with input signal and common-mode current nulling, provides a high input impedance level substantially independent of input capacitor size and input signal gain setting. An input voltage is sampled using one or more reference capacitor(s) that have been charged with a net charge corresponding to a quantizer-controlled reference voltage in a preceding clock phase. Since the charge pulled from the input voltage source is substantially determined only by the quantization error and input noise voltage, the circuit has a high input impedance. The reference capacitor(s) may be discharged in a third clock phase, so that input-signal-dependent voltages are discharged from the capacitor(s). An additional sampling capacitor can be discharged in the first clock phase and coupled in parallel with the reference capacitor during the second clock phase, to set the gain with respect to the input voltage.
摘要翻译： 具有输入信号和共模电流归零的离散时间可编程增益模数转换器（ADC）输入电路提供了基本上与输入电容大小和输入信号增益设置无关的高输入阻抗电平。 使用一个或多个参考电容对输入电压进行采样，该参考电容已经在前一时钟相位中与对应于量化器控制的参考电压的净电荷充电。 由于从输入电压源拉出的电荷基本上仅由量化误差和输入噪声电压确定，所以电路具有高的输入阻抗。 参考电容器可以在第三时钟相位中放电，使得输入信号相关电压从电容器放电。 在第二时钟相位期间，附加采样电容器可以在第一时钟相位放电并与参考电容并联耦合，以便相对于输入电压设置增益。
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公开(公告)号：US07151473B2
公开(公告)日：2006-12-19
申请号：US11203717
申请日：2005-08-15
IPC分类号： H03M1/84
摘要： A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver. In an embodiment, the in-phase analog-to-digital converter 112 and the in-phase digital filter 114 comprise an intermediate frequency receiver.
摘要翻译： 提供接收器100。 接收器100包括同相模拟数字转换器112，其可操作以检测同相模数转换器112的饱和状态，并调整由同相模数转换器112处理的同相信号的振幅 模数转换器112以从饱和状态除去同相模数转换器112;以及同相数字滤波器114，其可操作以调整施加到同相数字滤波器114的数字输入的增益 来自同相模数转换器112的增益基本上与由同相模数转换器112处理的同相信号的振幅的调整成反比。 在一个实施例中，接收器100还包括基本上类似于同相路径的正交路径，并且同相路径和正交路径包括直接转换接收器。 在一个实施例中，同相模数转换器112和同相数字滤波器114包括中频接收器。
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公开(公告)号：US20060071835A1
公开(公告)日：2006-04-06
申请号：US11240575
申请日：2005-10-03
申请人： Fumihito Inukai
发明人： Fumihito Inukai
IPC分类号： H03M3/00
摘要： A delta-sigma modulation circuit with a gain control function includes a variable gain amplifier, a control unit that controls the gain of the variable gain amplifier, a delta-sigma modulator that inputs an output from the variable gain amplifier, and a filter circuit that inputs an output from the delta-sigma modulator. The control unit that controls the gain of the variable gain amplifier gain controls the delta-sigma modulator. By this, the optimum dynamic range is obtained according to the setting level of the variable gain amplifier without causing the dynamic range to vary depending on the setting level of the variable gain amplifier.
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公开(公告)号：US20020126030A1
公开(公告)日：2002-09-12
申请号：US09845840
申请日：2001-04-30
发明人： Robert K. Perez , Norman J. Beamish
IPC分类号： H03M003/00
摘要： A variable gain coder-decoder is provided. The variable gain coder-decoder includes a variable gain amplifier in which the amplification gain may be adjusted in one-decibel steps. An analog to digital converter is connected to the variable gain amplifier. The analog to digital converter receives the amplified output of the amplifier, and performs an analog to digital conversion of the amplified output.
摘要翻译： 提供可变增益编码器解码器。 可变增益编码器 - 解码器包括可变增益放大器，其中放大增益可以以一分贝的步长进行调整。 模数转换器连接到可变增益放大器。 模数转换器接收放大器的放大输出，并执行放大输出的模数转换。
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公开(公告)号：US6037887A
公开(公告)日：2000-03-14
申请号：US611640
申请日：1996-03-06
申请人： Miaochen Wu , Timothy V. Kalthoff , Binan Wang
发明人： Miaochen Wu , Timothy V. Kalthoff , Binan Wang
摘要： A programmable gain delta sigma analog-to-digital converter includes an analog input terminal receiving an analog input voltage, a charge summing conductor, an input capacitive switching circuit, and a feedback reference capacitive switching circuit coupled to the charge summing conductor. An integrator is coupled between the charge summing conductor and a comparator which supplies a stream of digital pulses to a digital filter that produces a digital number representing the analog input voltage. The feedback reference capacitive switching circuit includes a plurality of reference sampling capacitors, selectively coupling charge between a feedback reference voltage source and an integrating capacitor of the integration in response to a programmable gain control circuit so as to provide a selected gain for the analog-to-digital converter. The sampling rate of the capacitive switching circuits is adjusted proportionally to the selected gain to improve the dynamic range of the analog-to-digital converter.
摘要翻译： 可编程增益ΔΣ模数转换器包括接收模拟输入电压的模拟输入端子，电荷求和导体，输入电容开关电路和耦合到电荷求和导体的反馈参考电容开关电路。 积分器耦合在电荷求和导体和比较器之间，比较器将数字脉冲流提供给产生代表模拟输入电压的数字数字的数字滤波器。 反馈参考电容开关电路包括多个参考采样电容器，响应于可编程增益控制电路，选择性地将反馈参考电压源和积分电容器之间的电荷耦合到一起，以便为模拟到 数字转换器 电容开关电路的采样率根据选定的增益进行调整，以改善模数转换器的动态范围。
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公开(公告)号：US5363102A
公开(公告)日：1994-11-08
申请号：US37300
申请日：1993-03-26
IPC分类号： H03M3/02
摘要： An IC chip formed with an analog-to-digital converter having a switched-capacitor programmable gain stage and employing a switched-capacitor sigma-delta modulator. The chip includes pins to receive a number of different audio input signals which are selectively connectible to buffer amplifiers the outputs of which are directed to a switch to select one output for further processing. The selected buffer amplifier output is d-c coupled to an input signal terminal of a switched-capacitor programmable gain stage. The output of this gain stage is coupled to an output stage including an op-amp and associated switched-capacitor circuitry. The programmable gain stage has a reference input terminal which is connected through an IC chip pin to an external capacitor the other electrode of which is returned to signal common. This capacitor develops a d-c voltage corresponding to the offset voltages of the operative buffer amplifier and the op-amp, and including a component corresponding to charge-injection from MOS switches. Absorption of such d-c voltages by this capacitor prevents those voltages from being significantly gained by the amplifier circuitry, and thereby prevents those voltages from using up an excessive portion of the dynamic range of the circuitry.
摘要翻译： 一种由具有开关电容可编程增益级并采用开关电容Σ-Δ调制器的模数转换器形成的IC芯片。 芯片包括用于接收多个不同音频输入信号的引脚，其可选择性地连接到缓冲放大器，其输出被引导到开关以选择一个输出用于进一步处理。 选择的缓冲放大器输出d-c耦合到开关电容可编程增益级的输入信号端。 该增益级的输出耦合到包括运算放大器和相关的开关电容器电路的输出级。 可编程增益级具有参考输入端，其通过IC芯片引脚连接到外部电容器，其另一个电极返回到信号共同。 该电容器产生对应于操作缓冲放大器和运算放大器的偏移电压的d-c电压，并且包括对应于MOS开关的电荷注入的分量。 通过该电容器吸收这种d-c电压可以防止放大器电路显着地获得这些电压，从而防止这些电压使电路的动态范围的过多部分使用。
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