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公开(公告)号：US4045608A
公开(公告)日：1977-08-30
申请号：US694349
申请日：1976-06-09
申请人： Robert A. Todd
发明人： Robert A. Todd
CPC分类号： F16D69/0408 , F16D69/021 , F16D69/026 , F16D2069/004 , F16D2069/0475 , Y10T428/213 , Y10T428/24995 , Y10T428/2907 , Y10T428/296 , Y10T428/2962 , Y10T428/31656 , Y10T428/31659 , Y10T428/31667 , Y10T428/31841 , Y10T428/31906
摘要： Porous friction facing materials containing cellulose fibers are coated with an impregnant of ethyl silicate to provide automatic transmission clutch plate and band linings of improved frictional properties, durability, wear and heat resistance, without use of asbestos. A sheet of paper-like fibrous material may be first impregnated with a phenolic resin binder which is cured to form a first coating and then impregnated with a hydrolyzed solution of ethyl silicate in a solvent. The material is further heated to drive off the solvent and cure the ethyl silicate to form a second outer coating having a higher coefficient of friction than the first coating. The silicate impregnated lining is then bonded to the steel plate or band. Alternatively, the resin impregnated lining material may be first bonded to the metal plate and then the entire plate assembly is impregnated with the ethyl silicate solution and cured.
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公开(公告)号：US20190146847A1
公开(公告)日：2019-05-16
申请号：US15873827
申请日：2018-01-17
申请人： Patrick D. Gibson , Robert A. Todd
发明人： Patrick D. Gibson , Robert A. Todd
IPC分类号： G06F9/50
摘要： Methods and apparatus for dynamic distributed resource management as can be used in large-scale electronic design automation processes, are disclosed. In some examples of the disclosed technology, a method for dynamic remote resource allocation includes receiving a request for one or more remote resources, identifying one or more resources available to satisfy the request, initiating one or more separate processes for the respective available resources, preparing the respective resources for use as remote resources, by the one or more separate processes running in parallel, and as a given resource of the one or more available resources completes the preparation, allocating the given resource as a remote resource. In some examples, allocated resources are dynamically integrated into the processing of the job. In some examples, as a given resource of the one or more available resources is allocated, tasking the given resource with a portion of the job.
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3.发明授权Method and apparatus for extracting and storing connectivity and geometrical data for a deep sub-micron integrated circuit design 失效用于提取和存储深亚微米集成电路设计的连接性和几何数据的方法和装置公开(公告)号：US06230299B1
公开(公告)日：2001-05-08
申请号：US09052895
申请日：1998-03-31
IPC分类号： G06S1750
CPC分类号： G06F17/5081
摘要： A data extraction tool is provided to extract filtered connectivity and geometrical data for specified layout cell hierarchies of an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The connectivity and geometrical data for each layout cell hierarchy are extracted at least in part in accordance with specified parasitic effect windows. In one embodiment, the data extraction tool includes a filtered extraction function that operates to extract connectivity and geometrical data for layout nets of each layout cell hierarchy of the IC design, one or more layout nets at a time. Additionally, one or more filtered databases are provided to store the filtered connectivity and geometrical data of the layout cell hierarchies.
摘要翻译： 提供数据提取工具来提取用于集成电路（IC）设计的指定布局单元层级的滤波连接性和几何数据。 深亚微米IC设计。 至少部分地根据指定的寄生效应窗口提取每个布局单元层级的连接性和几何数据。 在一个实施例中，数据提取工具包括滤波提取功能，其操作以提取用于IC设计的每个布局单元层次结构的布局网络的连接性和几何数据，一次一个或多个布局网。 另外，提供了一个或多个过滤的数据库以存储布局单元层次结构的经滤波的连接和几何数据。
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4.发明授权Method and apparatus for generating and maintaining electrical modeling data for a deep sub-micron integrated circuit design 失效用于生成和维护深亚微米集成电路设计的电气建模数据的方法和装置公开(公告)号：US06249903B1
公开(公告)日：2001-06-19
申请号：US09052915
申请日：1998-03-31
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A parasitic extraction tool (PEX) is provided to generate electrical modeling data for an integrated circuit (IC) design, e.g. a deep sub-micron IC design. The PEX includes a read function for reading extracted connectivity and geometrical data of various layout cell hierarchies of the IC design, that are organized and indexed by layout nets. The PEX also includes a write function for writing generated electrical modeling data into a parasitic database (PDB), which is physically organized to accommodate physical storage of the electrical modeling data in multiple physical media, and concurrent usage of the electrical data by multiple client applications, e.g. post layout analysis tool. In one embodiment, the PDB further includes an application interface that shields the physical organization of the PDB, and a logical abstraction of the physical organization to facilitate implementation of the application interface.
摘要翻译： 提供寄生提取工具（PEX）以产生集成电路（IC）设计的电气建模数据，例如。 深亚微米IC设计。 PEX包括用于读取提取的连接性和IC设计的各种布局单元层级的几何数据的读取功能，其由布局网组织和索引。 PEX还包括写入功能，用于将生成的电气建模数据写入到寄生数据库（PDB）中，寄生数据库（PDB）被物理组织以适应多个物理介质中的电气建模数据的物理存储，以及多个客户端应用程序的电气数据的并发使用 ，例如 后期布局分析工具。 在一个实施例中，PDB还包括屏蔽PDB的物理组织的应用接口以及物理组织的逻辑抽象以促进应用接口的实现。
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公开(公告)号：US20080235497A1
公开(公告)日：2008-09-25
申请号：US11945263
申请日：2007-11-26
IPC分类号： G06F9/315
CPC分类号： G06F17/5068
摘要： Multiple processing threads operate in parallel to convert data, produced by one or more electronic design automation processes in an initial format, into another data format for output. A processing thread accesses a portion of the initial results data produced by one or more electronic design automation processes in an initial format and in an initial organizational arrangement. The processing thread will then store data within this portion of the initial results data belonging to a target category of the desired output organizational arrangement, such as a cell, at a memory location corresponding to that target category. It will also convert the stored data from a first data format to another data format for output. The first data format may use a relatively low amount of compression, with the second data format may use a relatively high level of compression. Each of a plurality of processing threads may operate in this manner in parallel upon portions of the initial results data, until all of the initial results data has been converted to the desired data format for output. A processing thread can then collect the converted data from the various memory locations, and provide it as output data for the electronic design automation process or processes.
摘要翻译： 多个处理线程并行运行，将由一个或多个电子设计自动化过程产生的数据以初始格式转换成另一种数据格式进行输出。 处理线程以初始格式和初始组织布置访问由一个或多个电子设计自动化处理产生的初始结果数据的一部分。 然后，处理线程将在属于期望的输出组织布置的目标类别（例如单元）的初始结果数据的该部分内的数据存储在对应于该目标类别的存储器位置。 它还将存储的数据从第一个数据格式转换为另一个数据格式进行输出。 第一数据格式可以使用相对低的压缩量，第二数据格式可以使用相对较高的压缩级别。 多个处理线程中的每一个可以以这种方式在初始结果数据的一部分上并行操作，直到所有的初始结果数据已被转换为期望的数据格式以供输出。 然后，处理线程可以从各种存储器位置收集转换的数据，并将其提供为用于电子设计自动化过程或过程的输出数据。
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