公开(公告)号：US07659786B2

公开(公告)日：2010-02-09

申请号：US12043368

申请日：2008-03-06

申请人： Paul Bonwick ,  Alan Marshall ,  Howard Sims, legal representative

发明人： Paul Bonwick ,  Alan Marshall

IPC分类号： H03K3/03

CPC分类号： G01R31/3016 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/31937

摘要： A ring oscillator includes a first logic block having a first input connected to a specific point along a delay path, a first output and a second output, and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path, and a first output connected to the beginning of the delay path. The first logic block is arranged to alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to alternately select its first input and its second input every time a rising edge is input into its third input.

摘要翻译： 环形振荡器包括具有连接到沿着延迟路径的特定点的第一输入的第一逻辑块，第一输出和第二输出，以及具有连接到第一逻辑块的第一输出的第一输入的第二逻辑块， 连接到第一逻辑块的第二输出的第二输入，连接到延迟路径的末端的第三输入和连接到延迟路径的开头的第一输出。 第一逻辑块被布置为每当将上升沿输入到其第一输入时，将其第一输出和第二输出从逻辑高电平交替切换到逻辑低电平，反之亦然。 第二逻辑块被布置为每当将上升沿输入到其第三输入时交替地选择其第一输入及其第二输入。

公开(公告)号：US20120081148A1

公开(公告)日：2012-04-05

申请号：US12895370

申请日：2010-09-30

申请人： PAUL BONWICK

发明人： PAUL BONWICK

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： A programmable logic device includes a plurality of repeating units, each of which includes interconnecting lines, a logic block comprising logic circuits, and a configuration memory block including a plurality of configuration memory circuits. One of the plurality of repeating units includes: a selection device coupled to output data of the plurality of configuration memory circuits and a shift chain segment input; and a flip flop receiving output of the selection device to output a shift chain segment output.

摘要翻译： 可编程逻辑器件包括多个重复单元，每个重复单元包括互连线，包括逻辑电路的逻辑块和包括多个配置存储器电路的配置存储器块。 多个重复单元之一包括：耦合到多个配置存储器电路的输出数据的选择装置和移位链段输入; 触发器接收选择装置的输出以输出移位链段输出。

公开(公告)号：US07852115B2

公开(公告)日：2010-12-14

申请号：US12608499

申请日：2009-10-29

申请人： Paul Bonwick

发明人： Paul Bonwick

IPC分类号： H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/1778

摘要： A method and apparatus for connecting a load track (3) of a programmable interconnect to a plurality of intersecting driver tracks (2) of the programmable interconnect. The apparatus comprises a chain of connection cells (9;15), each connection cell being operable to connect the load track of the programmable interconnect to an associated intersecting driver track. Each cell also comprises connection signal receiving means arranged to receive a connection signal and activation signal receiving means arranged to receive an activation signal. The apparatus also comprises connection means arranged to connect the load track of the programmable interconnect to the associated intersecting driver track of the programmable interconnect when the connection signal receiving means has received a connection signal and the activation signal receiving means has received an activation signal. The apparatus also comprises activation signal propagating means arranged to propagate the activation signal to the next cell in the chain when the connection signal receiving means has not received a connection signal and the activation signal receiving means has received an activation signal.

摘要翻译： 一种用于将可编程互连的负载轨道（3）连接到可编程互连的多个相交的驱动器轨道（2）的方法和装置。 该设备包括连接单元链（9; 15），每个连接单元可操作以将可编程互连的负载轨道连接到相关联的交叉驱动器轨道。 每个单元还包括布置成接收连接信号的连接信号接收装置和布置成接收激活信号的激活信号接收装置。 该装置还包括连接装置，当连接信号接收装置已经接收到连接信号并且激活信号接收装置已经接收到激活信号时，连接装置将可编程互连的负载轨迹连接到可编程互连的相关联的交叉驱动器轨道。 该装置还包括当连接信号接收装置尚未接收到连接信号并且激活信号接收装置已经接收到激活信号时，激活信号传播装置被布置成将激活信号传播到链中的下一个小区。

公开(公告)号：US20100117681A1

公开(公告)日：2010-05-13

申请号：US12608499

申请日：2009-10-29

申请人： Paul BONWICK

发明人： Paul BONWICK

IPC分类号： H03K19/173 ,  H03K19/094

CPC分类号： H03K19/17736 ,  H03K19/1778

摘要： A method and apparatus for connecting a load track (3) of a programmable interconnect to a plurality of intersecting driver tracks (2) of the programmable interconnect. The apparatus comprises a chain of connection cells (9;15), each connection cell being operable to connect the load track of the programmable interconnect to an associated intersecting driver track. Each cell also comprises connection signal receiving means arranged to receive a connection signal and activation signal receiving means arranged to receive an activation signal. The apparatus also comprises connection means arranged to connect the load track of the programmable interconnect to the associated intersecting driver track of the programmable interconnect when the connection signal receiving means has received a connection signal and the activation signal receiving means has received an activation signal. The apparatus also comprises activation signal propagating means arranged to propagate the activation signal to the next cell in the chain when the connection signal receiving means has not received a connection signal and the activation signal receiving means has received an activation signal.

摘要翻译： 一种用于将可编程互连的负载轨道（3）连接到可编程互连的多个相交的驱动器轨道（2）的方法和装置。 该设备包括连接单元链（9; 15），每个连接单元可操作以将可编程互连的负载轨道连接到相关联的交叉驱动器轨道。 每个单元还包括布置成接收连接信号的连接信号接收装置和布置成接收激活信号的激活信号接收装置。 该装置还包括连接装置，当连接信号接收装置已经接收到连接信号并且激活信号接收装置已经接收到激活信号时，连接装置将可编程互连的负载轨迹连接到可编程互连的相关联的交叉驱动器轨道。 该装置还包括当连接信号接收装置尚未接收到连接信号并且激活信号接收装置已经接收到激活信号时，激活信号传播装置被布置成将激活信号传播到链中的下一个小区。

公开(公告)号：US20080309417A1

公开(公告)日：2008-12-18

申请号：US12043368

申请日：2008-03-06

申请人： Paul Bonwick ,  Alan Marshall ,  Howard Sims

发明人： Paul Bonwick ,  Alan Marshall ,  Howard Sims

IPC分类号： H03B1/00 ,  H03H11/26

CPC分类号： G01R31/3016 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/31937

摘要： A ring oscillator comprises a first logic block having a first input connected to a specific point along a delay path, a first output and a second output and a second logic block having a first input connected to the first output of the first logic block, a second input connected to the second output of the first logic block, a third input connected to the end of the delay path and a first output connected to the beginning of the delay path. The first logic block is arranged to, in use, alternately switch its first output and second output from logical HIGH to logical LOW, and vice versa, every time a rising edge is input into its first input. The second logic block is arranged to, in use, alternately select its first input and its second input every time a rising edge is input into its third input. The pulse width of the signal output from the first output of the second logic block is indicative of the time necessary for one of a rising edge or a falling edge to propagate from the beginning of the delay path to the specific point along the delay path and the inverse pulse width of the signal output from the first output of the second logic block is indicative of the time necessary for the one of the rising edge or the falling edge respectively to propagate from specific point along the delay path to the end of the delay path.

摘要翻译： 环形振荡器包括具有连接到沿着延迟路径的特定点的第一输入的第一逻辑块，第一输出和第二输出以及具有连接到第一逻辑块的第一输出的第一输入的第二逻辑块， 连接到第一逻辑块的第二输出的第二输入，连接到延迟路径的末端的第三输入和连接到延迟路径的开始的第一输出。 第一逻辑块被布置成在使用中，每当将上升沿输入到其第一输入时，交替地将其第一输出和第二输出从逻辑高电平切换到逻辑低电平，反之亦然。 第二逻辑块被布置成在使用中，每当将上升沿输入到其第三输入时，交替地选择其第一输入及其第二输入。 从第二逻辑块的第一输出输出的信号的脉冲宽度指示上升沿或下降沿中的一个从延迟路径的开始传播到沿延迟路径的特定点所需的时间， 从第二逻辑块的第一输出输出的信号的反向脉冲宽度指示上升沿或下降沿中的一个分别从沿着延迟路径的特定点传播到延迟结束所需的时间 路径。