公开(公告)号：US20220261308A1

公开(公告)日：2022-08-18

申请号：US17733627

申请日：2022-04-29

Applicant: Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

Inventor： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

IPC: G06F11/10 ,  G06F11/07 ,  G06F13/40

Abstract: Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

公开(公告)号：US20210232520A1

公开(公告)日：2021-07-29

申请号：US17231152

申请日：2021-04-15

Applicant: Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

Inventor： Swadesh Choudhary ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/38 ,  G06F13/40 ,  G06F11/10

Abstract: In one embodiment, an apparatus includes: a first link layer circuit to perform link layer functionality for a first communication protocol; and a logical physical (logPHY) circuit coupled to the first link layer circuit via a logical PHY interface (LPIF) link, the logPHY circuit to communicate with the first link layer circuit in a flit mode in which the first information is communicated in a fixed width size and to communicate with another link layer circuit in a non-flit mode. Other embodiments are described and claimed.

公开(公告)号：US20250123989A1

公开(公告)日：2025-04-17

申请号：US19000434

申请日：2024-12-23

Applicant: Swadesh CHOUDHARY ,  Debendra DAS SHARMA ,  Peter ONUFRYK ,  Lakshmipriya SESHAN

Inventor： Swadesh CHOUDHARY ,  Debendra DAS SHARMA ,  Peter ONUFRYK ,  Lakshmipriya SESHAN

IPC: G06F13/42

Abstract: This disclosure describes systems, methods, and devices related to priority packet optimization. For example, a system is described for sideband communication in a universal chiplet interconnect express (UCIe) environment. The system may include a sideband link may include a clock pin and a data pin configured to transmit auxiliary signals between chiplets. The system may include an encoding module configured to generate level-based encodings representing global event notifications. The system may include a notification propagation module configured to distribute global event notifications across a network topology interconnecting the chiplets.

公开(公告)号：US20220334995A1

公开(公告)日：2022-10-20

申请号：US17855687

申请日：2022-06-30

Applicant: Debendra Das Sharma ,  Mahesh S. Natu ,  Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan

Inventor： Debendra Das Sharma ,  Mahesh S. Natu ,  Sridhar Muthrasanallur ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan

IPC: G06F13/40 ,  G06F13/42

Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes a die-tio-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

公开(公告)号：US20190236038A1

公开(公告)日：2019-08-01

申请号：US16227364

申请日：2018-12-20

Applicant: Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

Inventor： Swadesh Choudhary ,  Bahaa Fahim ,  Doddaballapur Jayashimha ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

IPC: G06F13/20 ,  G06F13/40

CPC classification number: G06F13/20 ,  G06F13/4027

Abstract: Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes. The fabrics may comprise various topologies, including 2D mesh topologies and ring interconnect structures. Moreover, multi-level crediting and buffered mesh may be used for forwarding messages across dies.

公开(公告)号：US20220222198A1

公开(公告)日：2022-07-14

申请号：US17708367

申请日：2022-03-30

Applicant: Narasimha Lanka ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

Inventor： Narasimha Lanka ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

IPC: G06F13/42 ,  H01L25/065 ,  H01L23/538 ,  G06F13/40

Abstract: In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

公开(公告)号：US20220012140A1

公开(公告)日：2022-01-13

申请号：US17485180

申请日：2021-09-24

Applicant: Debendra Das Sharma ,  Michelle C. Jen ,  Swadesh Choudhary ,  Raghucharan Boddupalli

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Swadesh Choudhary ,  Raghucharan Boddupalli

IPC: G06F11/14 ,  G06F13/42

Abstract: A device includes a port with a replay buffer and protocol logic to receive a flit in a sequence of flits to be sent on a point-to-point link and determine an error in the flit. Based on the error, a copy of the flit is stored in a first position within the replay buffer as well as a copy of a next flit received in the sequence of flits, which is stored in a second position within the replay buffer. The copies of the flits are then written to a register for access by software.

公开(公告)号：US20210112132A1

公开(公告)日：2021-04-15

申请号：US17128648

申请日：2020-12-21

Applicant: NITISH PALIWAL ,  PEEYUSH PUROHIT ,  SWADESH CHOUDHARY ,  MANJULA PEDDIREDDY ,  MAHESH NATU ,  MAHESH WAGH

Inventor： NITISH PALIWAL ,  PEEYUSH PUROHIT ,  SWADESH CHOUDHARY ,  MANJULA PEDDIREDDY ,  MAHESH NATU ,  MAHESH WAGH

IPC: H04L29/08 ,  H04L12/741 ,  H04L12/863

Abstract: In one embodiment, an apparatus includes: a transaction layer circuit to output transaction layer information; and a link layer circuit coupled to the transaction layer circuit, the link layer circuit to receive and process the transaction layer information and to output link layer information to a physical circuit. The link layer circuit may include a first selection circuit to receive and direct cache memory protocol traffic to a selected one of a first logical port and a second logical port. Other embodiments are described and claimed.

公开(公告)号：US20200327084A1

公开(公告)日：2020-10-15

申请号：US16914327

申请日：2020-06-27

Applicant: Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

Inventor： Swadesh Choudhary ,  Robert G. Blankenship ,  Siva Prasad Gadey ,  Sailesh Kumar ,  Vinit Mathew Abraham ,  Yen-Cheng Liu

IPC: G06F13/40

Abstract: An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

公开(公告)号：US20200304150A1

公开(公告)日：2020-09-24

申请号：US16900637

申请日：2020-06-12

Applicant: Debendra Das Sharma ,  Swadesh Choudhary

Inventor： Debendra Das Sharma ,  Swadesh Choudhary

IPC: H03M13/15 ,  G06F13/42

Abstract: Embodiments herein describe a FEC codec for generating a check byte for a message. The FEC codec includes a port encoder having a storage unit, a Galois field multiplier, and a sum unit. The storage unit stores a first staged result, which is accumulated based on previous sets of input bytes of the message for all clock cycles from a first clock cycle to a clock cycle immediately prior to the current clock cycle. The Galois field multiplier performs a Galois field multiplication of the first staged result and a power of the alpha to generate a Galois field product. The sum unit performs a Galois field addition on an internal input based on a consolidated byte for the current clock cycle and the Galois field product to generate a second staged result for subsequent use to generate the check byte. Other embodiments may be described and/or claimed.