公开(公告)号：US06393502B1

公开(公告)日：2002-05-21

申请号：US09386650

申请日：1999-08-31

申请人： Derrick R. Meyer ,  Philip Enrique Madrid

发明人： Derrick R. Meyer ,  Philip Enrique Madrid

IPC分类号： G06F1314

CPC分类号： G06F13/4059

摘要： A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver. One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received. The remainder of the serial data stream is received at appropriate intervals of the second clock rate.

摘要翻译： 一种用于在具有不同时钟域的设备之间传送数据流的系统和方法。 该方法在发射机和接收机之间发起串行数据流。 发射机根据具有第一时钟速率的第一时钟进行操作，并且接收机根据具有第二时钟速率的第二时钟进行操作。 第二时钟速率和第一时钟速率之间的比率是大于或等于1的整数。 在发射机和接收机之间的串行线路上提供第一状态。 在串行线路上提供一个或多个起始位。 起始位表示与第一状态不同的第二状态。 在起始位之后，串行线上提供一个或多个比特比特。 比率比特指示第二时钟速率和第一时钟速率之间的比率。 接收到起始位。 在接收每个起始位时，使用第一状态和第二状态之间的转换是明显的，接收比率比特。 以第二时钟速率的适当间隔接收串行数据流的其余部分。

公开(公告)号：US06976122B1

公开(公告)日：2005-12-13

申请号：US10176771

申请日：2002-06-21

申请人： Benjamin Thomas Sander ,  Philip Enrique Madrid ,  Gregory William Smaus

发明人： Benjamin Thomas Sander ,  Philip Enrique Madrid ,  Gregory William Smaus

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F13/16

CPC分类号： G06F13/161 ,  G06F12/0215

摘要： A memory controller includes a threshold register that stores a value indicating a length of time and a control unit. In response to a first memory access request, the control unit generates signals that cause a memory device to open a page of memory. The control unit generates signals that cause the memory device to close the page if the page has been open for the length of time indicated by the value in the threshold register. The control unit modifies the value in the threshold register in response to receiving a second memory access request. For example, if the second memory access request causes a page miss for a most recently open page, the control unit may increase the value in the threshold register. The control unit may decrease the value in the threshold register in response to a page conflict caused by the second memory access request.

摘要翻译： 存储器控制器包括存储指示时间长度的值和控制单元的阈值寄存器。 响应于第一存储器访问请求，控制单元产生使存储器件打开一页存储器的信号。 如果页面已经在阈值寄存器中的值指示的时间长度上打开，则控制单元产生使存储器件关闭页面的信号。 响应于接收到第二存储器访问请求，控制单元修改阈值寄存器中的值。 例如，如果第二存储器访问请求导致最近打开页面的页面未命中，则控制单元可以增加阈值寄存器中的值。 控制单元可以响应于由第二存储器访问请求引起的页面冲突而减小阈值寄存器中的值。

公开(公告)号：US06505261B1

公开(公告)日：2003-01-07

申请号：US09428633

申请日：1999-10-27

申请人： Derrick R. Meyer ,  Philip Enrique Madrid

发明人： Derrick R. Meyer ,  Philip Enrique Madrid

IPC分类号： G06F104

CPC分类号： G06F13/4059

摘要： A system and method for inputting a set of values, e.g. an operating frequency, using dual-use signal connections. In an exemplary computer system, one or more processors are each coupled to a bridge. The dual-use signal connections are used to input an operating frequency ratio to a processor. The operating frequency ratio may also be input to the bridge. Once the operation of the processor has been initialized, the dual-use signal connections may be used to output operating parameters of the processor. The use of the using dual-use signal connections may advantageously allow for the operating frequency ratio to be input to the processor without dedicated signal lines or pins.

摘要翻译： 一种用于输入一组值的系统和方法，例如 一个工作频率，使用两用信号连接。 在示例性计算机系统中，一个或多个处理器各自耦合到桥。 双用途信号连接用于向处理器输入工作频率比。 工作频率比也可以输入到桥。 一旦处理器的操作被初始化，则可以使用双重用途信号连接来输出处理器的操作参数。 使用使用双重用途信号连接可以有利地允许将工作频率比率输入到处理器，而无需专用信号线或引脚。

公开(公告)号：US06760855B1

公开(公告)日：2004-07-06

申请号：US09594833

申请日：2000-06-14

申请人： William A. McGee ,  Philip Enrique Madrid

发明人： William A. McGee ,  Philip Enrique Madrid

IPC分类号： G06F118

CPC分类号： G06F13/4217 ,  G06F13/4072 ,  H03K5/133 ,  H03K2005/00156 ,  H03K2005/00234

摘要： The present invention relates to a method and related structure for reducing ground bounce during write operations from a microprocessor. More specifically, the address and data signal lines of the microprocessor are divided into three transmission groups. The first transmission group transitions its data onto the bus lines with no delay. The second transmission group transitions its signal lines onto the bus with a half clock period delay of the core frequency clock. Finally, the third transmission group transitions its signal lines onto the bus with a full clock period delay of the core frequency clock. In this way, parallel writes by the microprocessor have their current sinking associated with that write distributed over an entire clock period of the core frequency clock such that ground bounce associated with that current sinking is reduced.

摘要翻译： 本发明涉及一种用于在从微处理器写入操作期间减少接地反弹的方法和相关结构。 更具体地说，微处理器的地址和数据信号线被分成三个传输组。 第一传输组将其数据无延迟地转换到总线上。 第二传输组以核心频率时钟的半个时钟周期延迟将其信号线转换到总线上。 最后，第三个传输组以核心频率时钟的全时钟周期延迟将其信号线转换到总线上。 以这种方式，微处理器的并行写入使其电流吸收与在核心频率时钟的整个时钟周期分布的写入相关联，使得与该电流吸收相关联的接地反弹减小。

公开(公告)号：US06668292B2

公开(公告)日：2003-12-23

申请号：US10095019

申请日：2002-03-11

申请人： Derrick R. Meyer ,  Philip Enrique Madrid

发明人： Derrick R. Meyer ,  Philip Enrique Madrid

IPC分类号： G06F1314

CPC分类号： G06F13/4059

摘要： A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received. The remainder of the serial data stream is received at appropriate intervals of the second clock rate.

公开(公告)号：US06584575B1

公开(公告)日：2003-06-24

申请号：US09490307

申请日：2000-01-24

申请人： Deriick R. Meyer ,  Philip Enrique Madrid

发明人： Deriick R. Meyer ,  Philip Enrique Madrid

IPC分类号： G06F112

CPC分类号： G06F13/4059

摘要： A system and method for initializing deterministic source-synchronous transfers between devices in a computer system using one or more ratio bits to indicate a ratio between clocks. In an exemplary computer system, one or more processors are each coupled to a bridge. The one or more ratio bits are used to indicate a ratio between the system clock of a first device, such as a processor, and the system clock of a second device, such as the bridge. Each device may also operate at a multiple of its system clock. Once the one or more ratio bits have been stored, the first device can determine when edges of its operating clock correspond to edges of the operating clock of the second device. The use of the one or more ratio bits may advantageously allow devices in the computer system to operate on different system clocks without dedicated signal lines or pins to indicate the frequencies of those different system clocks.

摘要翻译： 一种用于使用一个或多个比特比特来初始化计算机系统中的设备之间的确定性源同步传输以指示时钟之间的比率的系统和方法。 在示例性计算机系统中，一个或多个处理器各自耦合到桥。 一个或多个比特比特用于指示诸如处理器的第一设备的系统时钟与诸如网桥的第二设备的系统时钟之间的比率。 每个设备也可以以其系统时钟的倍数工作。 一旦存储了一个或多个比特比特，则第一设备可以确定其工作时钟的边缘何时对应于第二设备的工作时钟的边缘。 使用一个或多个比特比特可以有利地允许计算机系统中的设备在不同的系统时钟上操作，而没有专用信号线或引脚来指示那些不同的系统时钟的频率。

公开(公告)号：US5732381A

公开(公告)日：1998-03-24

申请号：US618047

申请日：1996-03-25

申请人： Samuel James Guido ,  Rollie Morris Fisher ,  John Mark Wilson ,  Micah Charles Knapp ,  Gary Lynn Miller ,  Philip Enrique Madrid

发明人： Samuel James Guido ,  Rollie Morris Fisher ,  John Mark Wilson ,  Micah Charles Knapp ,  Gary Lynn Miller ,  Philip Enrique Madrid

IPC分类号： F02D41/34

CPC分类号： F02D41/345 ,  Y02T10/44

摘要： A method and system for generating a fuel pulse output signal to control fuel delivery from a fuel injector to a cylinder of an internal combustion engine. A plurality of holding registers asynchronously receive a plurality of fuel pulse data from a processor. The plurality of holding registers are memory-mapped and store the plurality of fuel pulse data until subsequent fuel pulse data is received from the processor. A plurality of match registers are coupled to the plurality of holding registers for comparing the fuel pulse data with a reference signal and generating a fuel pulse output signal based on the comparison between the fuel pulse data and the reference signal.

摘要翻译： 一种用于产生燃料脉冲输出信号以控制从燃料喷射器到内燃机的气缸的燃料传送的方法和系统。 多个保持寄存器从处理器异步接收多个燃料脉冲数据。 多个保持寄存器被存储器映射并存储多个燃料脉冲数据，直到从处理器接收到后续的燃料脉冲数据为止。 多个匹配寄存器耦合到多个保持寄存器，用于将燃料脉冲数据与参考信号进行比较，并且基于燃料脉冲数据与参考信号之间的比较产生燃料脉冲输出信号。