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1.发明授权System and method for handling exceptional instructions in a trace cache based processor 有权用于处理基于跟踪缓存的处理器中的异常指令的系统和方法公开(公告)号：US07133969B2
公开(公告)日：2006-11-07
申请号：US10676437
申请日：2003-10-01
申请人： Mitchell Alsup , Gregory William Smaus , James K. Pickett , Brian D. McMinn , Michael A. Filippo , Benjamin T. Sander
发明人： Mitchell Alsup , Gregory William Smaus , James K. Pickett , Brian D. McMinn , Michael A. Filippo , Benjamin T. Sander
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3861 , G06F12/0875
摘要： A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.
摘要翻译： 系统可以包括指令高速缓存，包括多个跟踪高速缓存条目的跟踪高速缓存以及耦合到指令高速缓存和跟踪高速缓存的跟踪发生器。 跟踪发生器可以被配置为接收由指令高速缓存输出的一组指令，用于存储在多个跟踪高速缓存条目之一中。 跟踪发生器可以被配置为检测指令组内的异常指令，并且防止异常指令被存储在多个跟踪高速缓存条目中的相同的一个跟踪高速缓存条目中，如任何非异常指令。
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2.发明授权Method and processor including logic for storing traces within a trace cache 有权方法和处理器包括用于在跟踪高速缓存中存储轨迹的逻辑公开(公告)号：US07213126B1
公开(公告)日：2007-05-01
申请号：US10755742
申请日：2004-01-12
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3806 , G06F9/3808 , G06F9/382 , G06F12/0875
摘要： A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.
摘要翻译： 处理器包括耦合到跟踪发生器的跟踪高速缓冲存储器。 跟踪发生器可以被配置为生成多个迹线，每个迹线包括可以从一个或多个指令解码的一个或多个操作。 每个操作可以与相应的地址相关联。 跟踪高速缓存存储器耦合到跟踪生成器，并且包括多个条目，每个条目被配置为存储跟踪的一个。 跟踪发生器还可以被配置为限制每个迹线仅包括具有落在连续地址的一个或多个预定范围内的相应地址的操作。
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公开(公告)号：US07610476B1
公开(公告)日：2009-10-27
申请号：US10729331
申请日：2003-12-05
CPC分类号： G06F9/28 , G06F9/30145 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control sequence logic unit. The microcode ROM may store multiple groups of microcode operations per row. For each group of microcode operations stored in a row, a corresponding control sequence may also be stored in the row. Each group of microcode operations may be included in a microcode routine. The groups of microcode operations stored in a row may be included in the same microcode routine, or some of the groups may be included in different microcode routines.
摘要翻译： 公开了用于存储多组微代码操作和每行微代码ROM的相应控制序列的方法和系统的各种实施例。 在一个实施例中，集成电路可以包括耦合到控制序列逻辑单元的微代码ROM。 微码ROM可以存储每行多组微代码操作。 对于存储在一行中的每组微代码操作，相应的控制序列也可以存储在该行中。 每组微代码操作可以包括在微代码程序中。 存储在一行中的微代码操作组可以包括在相同的微代码例程中，或者一些组可以被包括在不同的微代码例程中。
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公开(公告)号：US07555633B1
公开(公告)日：2009-06-30
申请号：US10700033
申请日：2003-11-03
CPC分类号： G06F9/3808 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F12/0862
摘要： Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a corresponding trace being evicted from the trace cache are disclosed. In some embodiments, a microprocessor may include an instruction cache, a trace cache, and a prefetch unit. In response to a trace being evicted from trace cache, the prefetch unit may fetch a line of instructions into instruction cache.
摘要翻译： 公开了用于实现微处理器的方法和系统的各种实施例，该微处理器响应于从跟踪高速缓存中逐出的对应跟踪而将指令组取入指令高速缓存。 在一些实施例中，微处理器可以包括指令高速缓存，跟踪高速缓存和预取单元。 响应于从跟踪缓存中被逐出的迹线，预取单元可以将指令行提取到指令高速缓存中。
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5.发明授权公开(公告)号：US08069336B2
公开(公告)日：2011-11-29
申请号：US10726902
申请日：2003-12-03
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/3802 , G06F9/3844
摘要： Various embodiments of methods and systems for implementing a microprocessor that includes a trace cache and attempts to transition fetching from instruction cache to trace cache only on label boundaries are disclosed. In one embodiment, a microprocessor may include an instruction cache, a branch prediction unit, and a trace cache. The prefetch unit may fetch instructions from the instruction cache until the branch prediction unit outputs a predicted target address for a branch instruction. When the branch prediction unit outputs a predicted target address, the prefetch unit may check for an entry matching the predicted target address in the trace cache. If a match is found, the prefetch unit may fetch one or more traces from the trace cache in lieu of fetching instructions from the instruction cache.
摘要翻译： 公开了用于实现微处理器的方法和系统的各种实施例，所述微处理器包括跟踪高速缓存并且仅在标签边界上尝试将指令高速缓存提取到跟踪高速缓存。 在一个实施例中，微处理器可以包括指令高速缓存，分支预测单元和跟踪高速缓存。 预取单元可以从指令高速缓存取出指令，直到分支预测单元输出分支指令的预测目标地址。 当分支预测单元输出预测的目标地址时，预取单元可以检查与跟踪高速缓存中的预测目标地址相匹配的条目。 如果找到匹配，则预取单元可以从跟踪高速缓存中取出一个或多个迹线，以代替从指令高速缓存取出指令。
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公开(公告)号：US20090106498A1
公开(公告)日：2009-04-23
申请号：US11877311
申请日：2007-10-23
申请人： Kevin Michael Lepak , Gregory William Smaus , William A. Hughes , Vydhyanathan Kalyanasundharam
发明人： Kevin Michael Lepak , Gregory William Smaus , William A. Hughes , Vydhyanathan Kalyanasundharam
IPC分类号： G06F13/28
CPC分类号： G06F12/0862 , G06F12/0815
摘要： A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission information is stored in the prefetch buffer. The corresponding prefetch data may be stored elsewhere. During a subsequent memory access request for a memory address stored in the prefetch buffer, both the coherency information and prefetched data may be already available and the memory access latency is reduced.
摘要翻译： 一种用于获取推测预取数据的一致性许可的系统和方法。 存储器控制器将预取存储器行的地址存储在预取缓冲器中。 在预取缓冲区中分配条目后，会发生系统中所有缓存的窥探。 一致性许可信息存储在预取缓冲区中。 相应的预取数据可以存储在别处。 在存储在预取缓冲器中的存储器地址的后续存储器访问请求期间，一致性信息和预取数据可能已经可用，并且存储器访问等待时间减少。
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公开(公告)号：US06976122B1
公开(公告)日：2005-12-13
申请号：US10176771
申请日：2002-06-21
CPC分类号： G06F13/161 , G06F12/0215
摘要： A memory controller includes a threshold register that stores a value indicating a length of time and a control unit. In response to a first memory access request, the control unit generates signals that cause a memory device to open a page of memory. The control unit generates signals that cause the memory device to close the page if the page has been open for the length of time indicated by the value in the threshold register. The control unit modifies the value in the threshold register in response to receiving a second memory access request. For example, if the second memory access request causes a page miss for a most recently open page, the control unit may increase the value in the threshold register. The control unit may decrease the value in the threshold register in response to a page conflict caused by the second memory access request.
摘要翻译： 存储器控制器包括存储指示时间长度的值和控制单元的阈值寄存器。 响应于第一存储器访问请求，控制单元产生使存储器件打开一页存储器的信号。 如果页面已经在阈值寄存器中的值指示的时间长度上打开，则控制单元产生使存储器件关闭页面的信号。 响应于接收到第二存储器访问请求，控制单元修改阈值寄存器中的值。 例如，如果第二存储器访问请求导致最近打开页面的页面未命中，则控制单元可以增加阈值寄存器中的值。 控制单元可以响应于由第二存储器访问请求引起的页面冲突而减小阈值寄存器中的值。
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