公开(公告)号：US20190244418A1

公开(公告)日：2019-08-08

申请号：US16269270

申请日：2019-02-06

申请人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC分类号： G06T15/80 ,  G06F9/50 ,  G06T1/20 ,  G06T5/20

CPC分类号： G06T15/80 ,  G06F9/50 ,  G06F9/5011 ,  G06T1/20 ,  G06T5/20

摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US07154502B2

公开(公告)日：2006-12-26

申请号：US10393514

申请日：2003-03-19

申请人： Philip R. Laws

发明人： Philip R. Laws

IPC分类号： G06T1/20 ,  G06T15/40 ,  G06F13/14

CPC分类号： G06T1/60 ,  G06T15/005 ,  G06T15/405

摘要： A 3D graphics architecture in which interfaces to memory are combined with pipeline processing. The rendering units are not all connected in a straight-through pipeline relationship: instead the rendering pipeline is “broken,” so that the stream of fragments (e.g. triangles) being processed is parked in memory. This turns out to be surprisingly efficient as a way to separate rendering processes where the workload balance is different. Preferably a first write to memory is performed after transformation and lighting calculations and before double-pass Z-buffering, and a second write to memory is performed before texturing. If Z-buffering or texturing is not being used for a particular rendering task, one or both of the memory interfaces can be switched off for that task. This economizes on memory bandwidth while retaining full flexibility.

摘要翻译： 一种3D图形架构，其中与存储器的接口与流水线处理相结合。 渲染单元并不都以直通管道关系连接：相反，渲染流水线被“破坏”，使得正在处理的片段流（例如三角形）被停放在存储器中。 事实证明，作为一种在工作负载平衡不同的渲染过程中进行分离的方法是非常有效的。 优选地，在转换和照明计算之后以及双遍Z缓冲之前执行对存储器的第一次写入，并且在纹理化之前执行对存储器的第二次写入。 如果Z缓冲或纹理不用于特定渲染任务，则可以关闭该任务中的一个或两个存储器接口。 这节省了内存带宽，同时保留了充分的灵活性。

公开(公告)号：US07106323B2

公开(公告)日：2006-09-12

申请号：US10071895

申请日：2002-02-08

申请人： Philip R. Laws ,  Jon Worthington

发明人： Philip R. Laws ,  Jon Worthington

IPC分类号： G06T15/00

CPC分类号： G06T15/20 ,  G06T2200/28

摘要： A set of techniques for rapidly computing a half-plane membership test for successive patches of pixels. By using an inheritance relation to carry forward values already computed at patch boundaries, the computational load for each successive patch is minimized. In a sample embodiment, just one interior point and one new boundary point are computed for each new patch of 64 pixels. Each of the 64 pixels can be described by an offset from one of the 5 reference points (i.e. the one interior point, the one newly computed boundary point, and 3 previously computed boundary points). By exploiting shift and complement relations, only a small number of offsets need to be independently computed (only 10 in this example). Since membership is determined merely by the sign of the relevant half-plane functions being computed, a simple compare between the half-plane function at the reference point and the half-plane function for the relevant offset suffices to evaluate the function's sign for that particular pixel.

公开(公告)号：US06587113B1

公开(公告)日：2003-07-01

申请号：US09591228

申请日：2000-06-09

申请人： David Robert Baldwin ,  Thomas Frommann ,  Philip R. Laws

发明人： David Robert Baldwin ,  Thomas Frommann ,  Philip R. Laws

IPC分类号： G09G536

CPC分类号： G06T15/005 ,  G06T1/60

摘要： A graphics processing unit in which the caching algorithm changes at the end of a line (or alternatively when the data from the beginning of the current line comes up for discard). This avoids the problem of continuous misses at the start of a new line, which can occur when the texture cache is not big enough to hold a full line's worth of data.

摘要翻译： 一个图形处理单元，其中高速缓存算法在一行的结尾改变（或者当来自当前行的开头的数据出现时丢弃）。 这避免了在新行开始时连续丢失的问题，当纹理缓存不够大以容纳整行的数据时，这可能会发生。