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公开(公告)号：US20190066354A1
公开(公告)日：2019-02-28
申请号：US15692951
申请日：2017-08-31
摘要： An apparatus and method are described for culling commands in a tile-based renderer. For example, one embodiment of an apparatus comprises: a command buffer to store a plurality of commands to be executed by a render pipeline to render a plurality of tiles; visibility analysis circuitry to determine per-tile visibility information for each of the plurality of tiles and to store the visibility information for a first tile in a first storage, the visibility information specifying either that all of the commands associated with rendering the first tile can be skipped or identifying individual commands associated with rendering the first tile that can be skipped; and a render pipeline to read the visibility information from the first storage to determine whether to execute or skip one or more of the commands from the command buffer to render the first tile.
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2.发明授权Dynamic programmable texture sampler for flexible filtering of graphical texture data 有权动态可编程纹理采样器，用于灵活过滤图形纹理数据公开(公告)号：US09355465B2
公开(公告)日：2016-05-31
申请号：US14142539
申请日：2013-12-27
摘要： For a given texture address, a multi-mode texture sampler fetches and reduces texture data with a multi-mode filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, filter coefficients specifying a weighting for each texel in a flexible footprint are cached from coefficient tables stored in memory. Techniques and systems are provided for dynamic allocation, update and handling of weighting coefficient tables as resources independent of sampler state.
摘要翻译： 对于给定的纹理地址，多模式纹理采样器使用多模式滤波器累加器来获取和减少纹理数据，该多模式滤波器累加器适用于在各种滤波器覆盖区域上提供加权平均。 多模式纹理采样器可配置为提供广泛的占位面积，并允许比双线性（2×2纹素）占地面积更大的滤波器占用面积。 在实施例中，从存储在存储器中的系数表缓存在柔性占用空间中指定每个纹素的加权的滤波器系数。 提供技术和系统用于动态分配，更新和处理加权系数表，作为独立于采样器状态的资源。
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3.发明申请DYNAMIC PROGRAMMABLE TEXTURE SAMPLER FOR FLEXIBLE FILTERING OF GRAPHICAL TEXTURE DATA 有权用于柔性过滤图形纹理数据的动态可编程纹理采样器公开(公告)号：US20150187089A1
公开(公告)日：2015-07-02
申请号：US14142539
申请日：2013-12-27
摘要： For a given texture address, a multi-mode texture sampler fetches and reduces texture data with a multi-mode filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, filter coefficients specifying a weighting for each texel in a flexible footprint are cached from coefficient tables stored in memory. Techniques and systems are provided for dynamic allocation, update and handling of weighting coefficient tables as resources independent of sampler state.
摘要翻译： 对于给定的纹理地址，多模式纹理采样器使用多模式滤波器累加器来获取和减少纹理数据，该多模式滤波器累加器适用于在各种滤波器覆盖区域上提供加权平均。 多模式纹理采样器可配置为提供广泛的占位面积，并允许比双线性（2×2纹素）占地面积更大的滤波器占用面积。 在实施例中，从存储在存储器中的系数表缓存在柔性占用空间中指定每个纹素的加权的滤波器系数。 提供技术和系统用于动态分配，更新和处理加权系数表，作为独立于采样器状态的资源。
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公开(公告)号：US20200074713A1
公开(公告)日：2020-03-05
申请号：US16116158
申请日：2018-08-29
申请人： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
发明人： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
摘要： Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
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公开(公告)号：US20190244418A1
公开(公告)日：2019-08-08
申请号：US16269270
申请日：2019-02-06
申请人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
发明人： Prasoonkumar Surti , Karthik Vaidyanathan , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh , Devan Burke , Philip R. Laws , Subramaniam Maiyuran , Abhishek R. Appu , ElMoustapha Ould-Ahmed-Vall , Peter L. Doyle
CPC分类号： G06T15/80 , G06F9/50 , G06F9/5011 , G06T1/20 , G06T5/20
摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.
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公开(公告)号：US10134314B2
公开(公告)日：2018-11-20
申请号：US13976012
申请日：2011-11-30
申请人： Michael Apodaca
发明人： Michael Apodaca
摘要： Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D application executing within a system or computing platform. 3D applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). These frames are then delivered to a display communicatively coupled with the system for rendering. Every display has a refresh rate specified in cycles per second or Hertz (Hz). Vertical Synchronization (VSYNC) is a setting that synchronizes the frames per second (FPS) of a given application with the display's refresh rate. Forcing VSYNC on the application while the system is operating on battery power may reduce the workload on the GPU when the FPS is greater than the refresh rate resulting in greater battery life.
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公开(公告)号：US09864638B2
公开(公告)日：2018-01-09
申请号：US13530250
申请日：2012-06-22
申请人： Michael Apodaca
发明人： Michael Apodaca
IPC分类号： G06F9/50 , G09G5/39 , G06F12/1009
CPC分类号： G06F9/5016 , G06F9/5044 , G06F12/1009 , G09G5/39 , Y02B70/16 , Y02D10/22
摘要： Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.
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公开(公告)号：US20170091989A1
公开(公告)日：2017-03-30
申请号：US14865933
申请日：2015-09-25
CPC分类号： G06T15/80 , G06F9/48 , G06F9/4881 , G06T1/20
摘要： By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.
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公开(公告)号：US20130271474A1
公开(公告)日：2013-10-17
申请号：US13976012
申请日：2011-11-30
申请人： Michael Apodaca
发明人： Michael Apodaca
IPC分类号： G09G3/00
CPC分类号： G09G3/001 , G06F1/3212 , G06F1/3265 , Y02D10/153 , Y02D10/174
摘要： Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D application executing within a system or computing platform. 3D applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). These frames are then delivered to a display communicatively coupled with the system for rendering. Every display has a refresh rate specified in cycles per second or Hertz (Hz). Vertical Synchronization (VSYNC) is a setting that synchronizes the frames per second (FPS) of a given application with the display's refresh rate. Forcing VSYNC on the application while the system is operating on battery power may reduce the workload on the GPU when the FPS is greater than the refresh rate resulting in greater battery life.
摘要翻译： 本文给出了各种实施例，其可以减少将视频数据帧传送到在系统或计算平台内执行的3D应用所生成的显示器的GPU所负责的工作量。 在系统内执行的3D应用可以以指定的帧速率（FPS）产生新的视频内容帧。 然后将这些帧传送到与系统通信地耦合以进行渲染的显示器。 每个显示器的刷新率都以每秒周期或赫兹（Hz）指定。 垂直同步（VSYNC）是一种使显示器刷新率同步给定应用程序的每秒帧数（FPS）的设置。 当系统使用电池供电时，在应用程序上强制VSYNC可能会在FPS大于刷新率导致更长的电池寿命时减少GPU上的工作量。
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公开(公告)号：US20190066255A1
公开(公告)日：2019-02-28
申请号：US15690201
申请日：2017-08-29
申请人： Hema Chand NALLURI , Balaji VEMBU , Peter DOYLE , Michael APODACA
发明人： Hema Chand NALLURI , Balaji VEMBU , Peter DOYLE , Michael APODACA
摘要： Various embodiments enable loop processing in a command processing block of the graphics hardware. Such hardware may include a processor including a command buffer, and a graphics command parser. The graphics command parser to load graphics commands from the command buffer, parse a first graphics command, store a loop count value associated with the first graphics command, parse a second graphics command and store a loop wrap address based on the second graphics command. The graphics command parser may execute a command sequence identified by the second graphics command, parse a third graphics command, the third graphics command identifying an end of the command sequence, set a new loop count value, and iteratively execute the command sequence using the loop wrap address based on the new loop count value.
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