公开(公告)号：US08860389B2

公开(公告)日：2014-10-14

申请号：US12649015

申请日：2009-12-29

Applicant: Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

Inventor： Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

IPC: G05F1/575 ,  G05F1/563

CPC classification number: G05F1/563

Abstract: A fast load transient response circuit includes a feedback loop that senses a load transient; a first driver and a second driver responsive to a feedback signal from the feedback loop; and a first pass transistor and a second pass transistor with sources and drains being coupled to each other, and a gate of the first pass transistor being driven by the first driver and a gate of the second pass transistor being driven by the second driver. A width of the channel to length of the channel (W/L) ratio of the first pass transistor is different than that of the second pass transistor such that second pass transistor reacts faster than the first pass transistors to a load transient.

Abstract translation: 快速负载瞬态响应电路包括感测负载瞬变的反馈回路; 响应于来自反馈回路的反馈信号的第一驱动器和第二驱动器; 以及第一传输晶体管和第二传输晶体管，其源极和漏极彼此耦合，并且第一传输晶体管的栅极由第一驱动器驱动，第二传输晶体管的栅极由第二驱动器驱动。 通道与第一通道晶体管的通道的宽度（W / L）比的宽度与第二传输晶体管的宽度不同，使得第二传输晶体管比第一传输晶体管更快地反应到负载瞬变。

公开(公告)号：US07679437B2

公开(公告)日：2010-03-16

申请号：US12043149

申请日：2008-03-06

Applicant: Preetam Charan Anand Tadeparthy ,  Vikram Gakhar

Inventor： Preetam Charan Anand Tadeparthy ,  Vikram Gakhar

IPC: H03F1/36

CPC classification number: H03F1/34 ,  H03F1/56 ,  H03F3/45475

Abstract: A circuit arrangement and method for improving load regulation in an amplifier (e.g., LDO amplifier) uses a feedback circuit including a parallely connected feedback resistance Rf and a noise reduction feedback capacitance Cf, wherein an external capacitance has equivalent series resistance (ESR). The circuit arrangement includes a resistance Resr in the amplifier output, a junction point of the feedback resistance Rf and the feedback capacitor Cf being connected to a negative input of the LDO amplifier. Additionally, the circuit arrangement might include a resistance Rintentional in between Cf and Rf. The circuit arrangement provides good load regulation and better stability without increase in power/area. The arrangement supports external feedback mode providing design flexibility without compromising amplifier-stability, which provides high output current drive capability or enables driving heavy output capacitance. In a preferred form the invention includes split feedback including AC feedback and DC feedback.

Abstract translation: 用于改善放大器（例如LDO放大器）中的负载调节的电路装置和方法使用包括平行连接的反馈电阻Rf和噪声降低反馈电容Cf的反馈电路，其中外部电容具有等效串联电阻（ESR）。 该电路装置包括放大器输出端的电阻Resr，反馈电阻Rf的连接点和反馈电容器Cf连接到LDO放大器的负输入端。 另外，电路装置可能包括在Cf和Rf之间的电阻Rintentional。 电路布置提供良好的负载调节和更好的稳定性，而不增加功率/面积。 该布置支持外部反馈模式，提供设计灵活性，而不会影响放大器稳定性，这提供高输出电流驱动能力或实现驱动大输出电容。 在优选形式中，本发明包括包括AC反馈和DC反馈的分离反馈。

公开(公告)号：US09594387B2

公开(公告)日：2017-03-14

申请号：US13235529

申请日：2011-09-19

Applicant: Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

Inventor： Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

IPC: G05F1/10 ,  G05F1/575 ,  H02M1/36 ,  G05F1/46

CPC classification number: G05F1/575 ,  G05F1/468 ,  H02M1/36

Abstract: A voltage regulator includes a measurement circuit for obtaining a value representing a magnitude of an output capacitance connected at an output node of the voltage regulator. A correction circuit in the voltage regulator modifies a compensation circuit internal to the voltage regulator based on the value. The modification of the compensation circuit is done to ensure that sufficient stability margins to accommodate the output capacitance are ensured for the main feedback loop in the voltage regulator. In an embodiment, a voltage proportional to the output capacitance is detected at start-up of the voltage regulator, and a corresponding binary signal is generated. The logic value of the binary signal is used to add or remove components and/or circuit portions in the compensation circuit to ensure stability. The voltage regulator is thus designed to support a wide range of output capacitance values.

Abstract translation: 电压调节器包括用于获得表示在电压调节器的输出节点处连接的输出电容的幅度的值的测量电路。 电压调节器中的校正电路根据该值修改电压调节器内部的补偿电路。 完成补偿电路的修改以确保为稳压器中的主反馈环路确保足够的稳定裕度以适应输出电容。 在一个实施例中，在电压调节器的启动时检测与输出电容成比例的电压，并且产生相应的二进制信号。 二进制信号的逻辑值用于在补偿电路中添加或删除组件和/或电路部分以确保稳定性。 因此，电压调节器被设计成支持宽范围的输出电容值。

公开(公告)号：US08115337B2

公开(公告)日：2012-02-14

申请号：US12325625

申请日：2008-12-01

Applicant: Preetam Charan Anand Tadeparthy

Inventor： Preetam Charan Anand Tadeparthy

IPC: H02J4/00

CPC classification number: H02M1/32 ,  G05F1/573 ,  H02M1/36 ,  Y10T307/549 ,  Y10T307/735

Abstract: An apparatus is provided. The apparatus comprises an input circuit, a startup circuit, and a current limiter. The input circuit is coupled to a first source and is adapted to provide a first voltage and a first current to a load having a capacitance. The startup circuit is coupled to the input circuit and to the first source, and the startup circuit includes a current source and a startup capacitor coupled in series with one another. The current limiter has a cascode circuit and a discharge circuit. The cascode circuit has a bias transistor and a power transistor coupled in series with one another to provide a second voltage and a second current to the load, where the bias transistor is coupled to a second source and where the bias transistor generally operates as source follower during startup. The discharge circuit is coupled to a node between the bias transistor and the power transistor of the cascode circuit and coupled to a node between the startup current source.

Abstract translation: 提供了一种装置。 该装置包括输入电路，启动电路和限流器。 输入电路耦合到第一源并且适于向具有电容的负载提供第一电压和第一电流。 启动电路耦合到输入电路和第一源，并且启动电路包括彼此串联耦合的电流源和启动电容器。 限流器具有共源共栅电路和放电电路。 共源共栅电路具有彼此串联耦合的偏置晶体管和功率晶体管，以向负载提供第二电压和第二电流，其中偏置晶体管耦合到第二源，并且偏置晶体管通常作为源极跟随器 在启动期间。 放电电路耦合到偏置晶体管和共源共栅电路的功率晶体管之间的节点，并耦合到启动电流源之间的节点。

公开(公告)号：US20110156671A1

公开(公告)日：2011-06-30

申请号：US12649015

申请日：2009-12-29

Applicant: Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

Inventor： Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

IPC: G05F1/565

CPC classification number: G05F1/563

Abstract: A fast load transient response circuit includes a feedback loop that senses a load transient; a first driver and a second driver responsive to a feedback signal from the feedback loop; and a first pass transistor and a second pass transistor with sources and drains being coupled to each other, and a gate of the first pass transistor being driven by the first driver and a gate of the second pass transistor being driven by the second driver. A width of the channel to length of the channel (W/L) ratio of the first pass transistor is different than that of the second pass transistor such that second pass transistor reacts faster than the first pass transistors to a load transient.

Abstract translation: 快速负载瞬态响应电路包括感测负载瞬变的反馈回路; 响应于来自反馈回路的反馈信号的第一驱动器和第二驱动器; 以及第一传输晶体管和第二传输晶体管，其源极和漏极彼此耦合，并且第一传输晶体管的栅极由第一驱动器驱动，第二传输晶体管的栅极由第二驱动器驱动。 通道与第一通道晶体管的通道的宽度（W / L）比的宽度与第二传输晶体管的宽度不同，使得第二传输晶体管比第一传输晶体管更快地反应到负载瞬变。

公开(公告)号：US07733180B1

公开(公告)日：2010-06-08

申请号：US12323813

申请日：2008-11-26

Applicant: Preetam Charan Anand Tadeparthy ,  Vikram Gakhar

Inventor： Preetam Charan Anand Tadeparthy ,  Vikram Gakhar

IPC: H03F3/45

CPC classification number: H03F3/505 ,  H03F3/45475 ,  H03F2200/297

Abstract: An apparatus having a zero-pole that is dependant on an equivalent series resistance (ESR) and a load is provided. The apparatus comprises an amplifier stage that receives a first input voltage and a bias voltage, an intermediate stage that is coupled to the output node of the amplifier stage (where the intermediate stage outputs an intermediate voltage to an intermediate node), a first capacitor coupled between at least one of the internal transistors at an internal node and the intermediate node, a power transistor coupled between a second input voltage and the intermediate node, a second capacitor coupled between the internal node and the power transistor, and a feedback stage coupled to the intermediate node and to the amplifier stage. The amplifier stage also has an output node and includes a plurality of internal transistors. The second capacitor provides a third input voltage to the power transistor, and the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor controls the position of the zero-pole. Additionally, the feedback stage is adapted to output an output voltage to a load, and wherein the feedback stage provides a feedback voltage to the amplifier stage.

Abstract translation: 具有取决于等效串联电阻（ESR）和负载的零极的装置。 该装置包括接收第一输入电压和偏置电压的放大器级，耦合到放大器级的输出节点（其中中间级向中间节点输出中间电压）的中间级，第一电容器耦合 在内部节点处的至少一个内部晶体管和中间节点之间，耦合在第二输入电压和中间节点之间的功率晶体管，耦合在内部节点和功率晶体管之间的第二电容器，以及耦合到 中间节点和放大器级。 放大器级还具有输出节点并且包括多个内部晶体管。 第二电容器向功率晶体管提供第三输入电压，并且第一电容器的电容与第二电容器的电容的比率控制零极的位置。 此外，反馈级适于将输出电压输出到负载，并且其中反馈级向放大器级提供反馈电压。

公开(公告)号：US07417574B2

公开(公告)日：2008-08-26

申请号：US11162982

申请日：2005-09-30

Applicant: Preetam Charan Anand Tadeparthy ,  Jomy G. Joy

Inventor： Preetam Charan Anand Tadeparthy ,  Jomy G. Joy

IPC: H03M1/12

CPC classification number: H03M1/1225 ,  H03M1/167

Abstract: An analog to digital converter (ADC) containing an operational amplifier having a first pair of input terminals and a second pair of input terminals, wherein the output varies if the input signals on either of the input terminals pairs is changed in either the sampling phase or a hold phase. Such an operational amplifier is conveniently shared by two stages of a ADC, while reducing power consumption as well as errors.

Abstract translation: 一种包含运算放大器的模数转换器（ADC），该运算放大器具有第一对输入端和第二对输入端，其中如果任一输入端对上的输入信号在采样相位或者采样相位中改变，则输出变化 保持阶段 这样的运算放大器可以方便地由ADC的两级共享，同时降低功耗以及错误。

公开(公告)号：US07126523B2

公开(公告)日：2006-10-24

申请号：US11163901

申请日：2005-11-03

Applicant: Preetam Charan Anand Tadeparthy

Inventor： Preetam Charan Anand Tadeparthy

IPC: H03M1/34

CPC classification number: H03M1/1225 ,  H03M1/167

Abstract: An amplifier sharing technique in an analog to digital converter (ADC) in which a cascaded combination of a pre-amplifier and main amplifier is used to provide the required amplification for a first stage, and only the main amplifier is used to provide the amplification for the second stage. Switches and capacitors are used in conjunction such that the sampling and feedback capacitors of the first stage are connected across the cascaded combination in a first phase, and sampling and feedback capacitors of the second stage are connected across the main amplifier in a second phase. By appropriate choice of parameter values for various components, the second poles due to the pre-amplifier may be located at the higher frequency ranges obtaining the required unity gain bandwidth (UGB) without Miller compensation and/or additional gain.

Abstract translation: 在模数转换器（ADC）中的放大器共享技术，其中前置放大器和主放大器的级联组合用于为第一级提供所需的放大，并且仅使用主放大器来提供放大 第二阶段 开关和电容器结合使用，使得第一级的采样和反馈电容器在第一阶段跨越级联组合连接，第二级的采样和反馈电容器在第二阶段跨主放大器连接。 通过适当选择各种组件的参数值，由前置放大器引起的第二极可以位于较高的频率范围，从而获得不需要米勒补偿和/或附加增益的所需单位增益带宽（UGB）。

公开(公告)号：US08773095B2

公开(公告)日：2014-07-08

申请号：US12649035

申请日：2009-12-29

Applicant: Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

Inventor： Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

IPC: G05F1/00

CPC classification number: G05F1/565 ,  H02H9/001 ,  H02M1/32 ,  H02M1/36 ,  H02M3/155 ,  H02M2001/0045

Abstract: A startup circuit in an LDO includes an operational amplifier having an inverting terminal and a non-inverting terminal and an output node. The non-inverting terminal receives a reference voltage. The startup circuit further includes a feedback capacitor coupled between an output node and the inverting terminal and a current source coupled between the inverting terminal and ground such that the current source and the feedback capacitor together control rate of change of an output voltage of the operational amplifier. A comparator is used to stop the rate of change of output voltage after the output voltage reaches a desired value.

Abstract translation: LDO中的启动电路包括具有反相端和反相端的运算放大器和输出节点。 同相端子接收参考电压。 启动电路还包括耦合在输出节点和反相端子之间的反馈电容器和耦合在反相端子和接地之间的电流源，使得电流源和反馈电容器一起控制运算放大器的输出电压的变化率 。 比较器用于在输出电压达到所需值之后停止输出电压的变化率。

公开(公告)号：US08536934B1

公开(公告)日：2013-09-17

申请号：US13402898

申请日：2012-02-23

Applicant: Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

Inventor： Vikram Gakhar ,  Preetam Charan Anand Tadeparthy

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: A linear voltage regulator includes a pair of amplifiers. A first amplifier of the pair is used in conventional fashion to generate a regulated output voltage by controlling an impedance of a pass transistor in the linear voltage regulator, the controlling being based on a difference between a reference voltage and a voltage at a first node in a voltage divider network connected between the output terminal of the voltage regulator and a ground terminal. The second amplifier of the pair compares the regulated output voltage and a voltage at a second node in the voltage divider network, and injects a proportional current into the first node. Generation of a regulated output voltage lesser than the reference voltage is thereby enabled.

Abstract translation: 线性稳压器包括一对放大器。 该对的第一放大器以常规方式用于通过控制线性稳压器中的通过晶体管的阻抗来产生调节的输出电压，该控制基于参考电压和第一节点处的电压之间的差 连接在电压调节器的输出端子与接地端子之间的分压网络。 该对的第二放大器将调节输出电压和分压器网络中的第二节点处的电压进行比较，并将比例电流注入到第一节点中。 从而能够产生小于参考电压的稳压输出电压。