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12 条记录 (耗时 0.017 秒)

    Card guide for expansion circuit card
    1.
    发明授权
    Card guide for expansion circuit card 失效
    扩展电路卡

    公开(公告)号：US07187555B2

    公开(公告)日：2007-03-06

    申请号：US10458008

    申请日：2003-06-10

    申请人： Robert G. Campbell ,  Raymond Chin

    发明人： Robert G. Campbell ,  Raymond Chin

    IPC分类号： H05K5/00

    CPC分类号： G06F1/185 ,  G06F1/184 ,  G06F1/186

    摘要： An apparatus in one example comprises a card guide that provides an installation path for an extension circuit card. The installation path promotes a coupled relationship between the extension circuit card and a circuit board. The card guide comprises a first connector and a second connector. To form the coupled relationship the extension circuit card attaches to one of the first connector and the second connector based on a configuration of the extension circuit card.

    摘要翻译： 一个示例中的装置包括提供扩展电路卡的安装路径的卡引导件。 安装路径促进了扩展电路卡和电路板之间的耦合关系。 卡引导件包括第一连接器和第二连接器。 为了形成耦合关系，扩展电路卡基于扩展电路卡的配置连接到第一连接器和第二连接器之一。

    Selectively operating a host's device controller in a first mode or a second mode
    2.
    发明授权
    Selectively operating a host's device controller in a first mode or a second mode 失效
    以第一模式或第二模式选择性地操作主机的设备控制器

    公开(公告)号：US06701402B1

    公开(公告)日：2004-03-02

    申请号：US09820727

    申请日：2001-03-30

    申请人： Walter W. Alexander, III ,  Wesley H. Stelter ,  Robert G. Campbell

    发明人： Walter W. Alexander, III ,  Wesley H. Stelter ,  Robert G. Campbell

    IPC分类号： G06F1314

    CPC分类号： G06F3/0626 ,  G06F3/0658 ,  G06F3/0689

    摘要： The present invention includes an integrated circuit that is operable to connect a redundant array of inexpensive disks (RAID) or other peripheral device to a disk controller, such as a small computer system interface (SCSI) controller in a host device. The integrated circuit provides the peripheral device with sole access to the disk controller when operating in a straight mode. In straight mode, the peripheral device may communicate with the disk controller through a PCI bus to perform operations, such as retrieving or writing data to the peripheral device. Also, when in straight mode, other controllers, including the host's CPU, may be prevented from using the disk controller to avoid data collisions, data loss and possible system failure. The integrated circuit may also function in standard mode, such that other controllers connected to the host may access the disk controller.

    摘要翻译： 本发明包括集成电路，其可操作以将廉价磁盘（RAID）或其他外围设备的冗余阵列连接到诸如主机设备中的小型计算机系统接口（SCSI）控制器的磁盘控制器。 集成电路使得外围设备在以直线模式操作时能够唯一地访问磁盘控制器。 在直模式中，外围设备可以通过PCI总线与盘控制器进行通信，以执行操作，例如将数据检索或写入外围设备。 另外，当处于直接模式时，可能会阻止包括主机CPU在内的其他控制器使用磁盘控制器来避免数据冲突，数据丢失和可能的系统故障。 集成电路还可以在标准模式下工作，使得连接到主机的其他控制器可以访问磁盘控制器。

    Debris receptacle, cover, and contents compressor and discharge assembly
    3.
    发明授权
    Debris receptacle, cover, and contents compressor and discharge assembly 失效
    碎片容器，盖子和内容物压缩机和排放组件

    公开(公告)号：US4440321A

    公开(公告)日：1984-04-03

    申请号：US389451

    申请日：1982-06-16

    申请人： Robert G. Campbell ,  Warren A. Campbell, III

    发明人： Robert G. Campbell ,  Warren A. Campbell, III

    IPC分类号： B65F1/12 ,  B67D5/32 ,  B65D90/00

    CPC分类号： B65F1/12 ,  B65F2240/138 ,  Y10S206/815 ,  Y10S220/908

    摘要： A receptacle and cover assembly for collecting lawn debris and the like and including structure for assisting transfer of compacted contents of the receptacle to expendable lawn trash bags and the like, comprising a main receptacle body section in the shape of an upwardly opening container having a skirt-like lower edge formation at the bottom of the receptacle body section for supporting it in upright position, and a removable cover member for the receptacle body section. The body section has a centrally open outer bottom wall portion extending inwardly from the side wall at a position spaced slightly above the lower edge formation providing a shelf-like ledge extending inwardly from the side wall, and a moveable bottom panel member forming a discharge assist piston which rests on shelf-like ledge formation and collectively therewith forms the bottom of the receptacle. The center opening in the bottom wall portion is large enough for passage of the operator's hand therethrough to manually engage and force the bottom panel member toward the open upper end of the receptacle when the cover is removed and an expendable debris collecting bag is fitted over the receptacle to facilitate transfer of the contents of the body section into the expendable bag.

    摘要翻译： 用于收集草坪碎屑等的容器和盖组件，并且包括用于辅助将容器的压实内容物转移到消耗性草坪垃圾袋等的结构，包括具有裙部的向上开口的容器的主容器主体部分 在容器主体部分的底部形成用于将其支撑在直立位置的下边缘形状，以及用于插座主体部分的可移除的盖部件。 主体部分具有中央打开的外底壁部分，该中部开口的外底壁部分在距离下边缘部分稍微上方的位置处从侧壁向内延伸，提供从侧壁向内延伸的搁架状突出部，以及形成排出辅助 活塞位于搁架状突起形成上并且一起形成容器的底部。 底壁部分中的中心开口足够大以使操作者的手通过，以便当盖被移除时手动接合并迫使底板构件朝向容器的敞开的上端，并且将消耗性碎屑收集袋安装在 容器以便于将身体部分的内容物转移到消耗品袋中。

    Clock distribution in multi-cell computing systems
    6.
    发明授权
    Clock distribution in multi-cell computing systems 有权
    多单元计算系统中的时钟分布

    公开(公告)号：US07478255B2

    公开(公告)日：2009-01-13

    申请号：US11304370

    申请日：2005-12-13

    申请人： Robert G. Campbell ,  Spencer Frink

    发明人： Robert G. Campbell ,  Spencer Frink

    IPC分类号： G06F1/12

    CPC分类号： G06F1/10

    摘要： Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. A clock source provides a clock to a switch, which replicates the clock and provides the replicated clocks to its ports. Each port of the switch, receiving a replicated clock, encodes this replicated clock and sends it over a link to each agent of a cell. Each agent of the cells, receiving an encoded clock, decodes this encoded clock, resulting in a decoded, or an extracted, clock. The agent then replicates the extracted clock and provides the replicates of the extracted clock to a plurality of CPUs of the cell. As a result, CPUs in all cells of the system receive clocks that all are synchronized to the clock provided by the clock source. Other embodiments are also disclosed including using the extracted clock as phase information, scaling, redundancy, etc.

    摘要翻译： 本发明的实施例涉及在处理多小区系统的小区中将时钟分配给CPU。 在一个实施例中，每个小区包括被称为代理的接口。 称为开关的多个接口与单元的代理一起将单元连接在一起。 时钟源为交换机提供时钟，它复制时钟，并向其端口提供复制时钟。 交换机的每个端口，接收复制的时钟，对这个复制的时钟进行编码，并将其通过链路发送到单元的每个代理。 接收编码时钟的单元的每个代理解码该编码时钟，导致解码或提取的时钟。 然后，代理复制提取的时钟，并将提取的时钟的重复提供给小区的多个CPU。 因此，系统的所有单元中的CPU都会接收与时钟源提供的时钟同步的时钟。 还公开了其他实施例，包括使用提取的时钟作为相位信息，缩放，冗余等

    Method and system for updating a value of a slow register to a value of a fast register
    7.
    发明授权
    Method and system for updating a value of a slow register to a value of a fast register 失效
    用于将慢速寄存器的值更新为快速寄存器的值的方法和系统

    公开(公告)号：US07437587B2

    公开(公告)日：2008-10-14

    申请号：US11040756

    申请日：2005-01-21

    申请人： Robert G. Campbell

    发明人： Robert G. Campbell

    IPC分类号： G06F1/12 ,  G06F1/00

    CPC分类号： G06F9/3869 ,  G06F1/14 ,  G06F9/3885

    摘要： Embodiments of the invention relate to synchronizing registers. An embodiment includes a plurality of processing cells each includes a plurality of CPUs, which run at different frequencies and each of which has an ar.itc timer register. A CPU in the fastest cell of the plurality of cells is referred to as the fast CPU. CPUs in slower cells are referred to as slow CPUs. At predetermined time intervals, slow CPUs are provided with the ar.itc value of the fast CPU to replace the values of their ar.itc. As a result, values in the ar.itc registers are synchronized without providing negative time. Other embodiments are also disclosed.

    摘要翻译： 本发明的实施例涉及同步寄存器。 一个实施例包括多个处理单元，每个处理单元包括多个CPU，其以不同的频率运行，并且每个具有一个定时器寄存器。 多个单元中最快单元中的CPU被称为快速CPU。 较慢单元格中的CPU被称为缓慢的CPU。 以预定的时间间隔，缓慢的CPU提供快速CPU的ar.itc值来替换其ar.itc的值。 因此，ar.itc寄存器中的值将同步而不会提供负时间。 还公开了其他实施例。

    Assigning PCI device interrupts in a computer system
    8.
    发明授权
    Assigning PCI device interrupts in a computer system 失效
    在计算机系统中分配PCI设备中断

    公开(公告)号：US06636916B1

    公开(公告)日：2003-10-21

    申请号：US09503749

    申请日：2000-02-14

    申请人： Robert G. Campbell ,  Wesley H. Stelter

    发明人： Robert G. Campbell ,  Wesley H. Stelter

    IPC分类号： G06F1324

    CPC分类号： G06F13/24

    摘要： A method and apparatus for assigning interrupts to devices on a PCI bus in a computer system in which a plurality of address lines are channeled through a multiplexer to a PCI device on the PCI bus. The multiplexer enables the user to dynamically select which address line is routed to the IDSEL pin on the PCI device. According to the PCI specification, the address line connected to the IDSEL pin determines the Device ID for that PCI device. In turn, the Device ID establishes which of the four available interrupt INT# lines are assigned to that PCI device. Thus, the interrupt INT# line assignments can be dynamically controlled. Where desired, the user can force two PCI devices to share an interrupt line, or the user can force the devices to use separate interrupts.

    摘要翻译： 一种用于将计算机系统中的PCI总线上的设备分配中断的方法和装置，其中多个地址线通过多路复用器被引导到PCI总线上的PCI设备。 多路复用器使用户能够动态地选择哪个地址线路由到PCI设备上的IDSEL引脚。 根据PCI规范，连接到IDSEL引脚的地址线确定该PCI设备的设备ID。 反过来，器件ID建立四个可用中断INT＃线中哪一个被分配给该PCI设备。 因此，可以动态地控制中断INT＃行分配。 如果需要，用户可以强制两个PCI设备共享中断线，或者用户可以强制设备使用单独的中断。

    Minimizing signal stub length for high speed busses
    9.
    发明授权
    Minimizing signal stub length for high speed busses 失效
    最大限度地减少高速总线的信号短线长度

    公开(公告)号：US06601125B1

    公开(公告)日：2003-07-29

    申请号：US09528757

    申请日：2000-03-17

    申请人： Robert G Campbell

    发明人： Robert G Campbell

    IPC分类号： G06F1314

    CPC分类号： H01L23/66 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2224/45099

    摘要： An integrated circuit package for electrically interconnecting a first bus signal path disposed on a printed circuit board and a second bus signal path disposed on the printed circuit board. The integrated circuit package may have a substrate, an integrated circuit chip die supported by the substrate. The interconnection network may be for electrically connecting the first bus signal path and the second bus signal path to a chip pad on the chip die. Thus, the first bus signal path and the second bus signal path may be electrically interconnected by only the interconnection circuit.

    摘要翻译： 一种集成电路封装，用于将布置在印刷电路板上的第一总线信号路径和布置在印刷电路板上的第二总线信号路径电互连。 集成电路封装可以具有衬底，由衬底支撑的集成电路芯片裸片。 互连网络可以用于将第一总线信号路径和第二总线信号路径电连接到芯片芯片上的芯片焊盘。 因此，第一总线信号路径和第二总线信号路径可以仅由互连电路电互连。