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    Systems, apparatuses, and methods for arithmetic recurrence
    1.
    发明授权
    Systems, apparatuses, and methods for arithmetic recurrence 有权

    公开(公告)号：US10120680B2

    公开(公告)日：2018-11-06

    申请号：US15396184

    申请日：2016-12-30

    申请人： Rama Kishan V. Malladi ,  Elmoustapha Ould-Ahmed-Vall

    发明人： Rama Kishan V. Malladi ,  Elmoustapha Ould-Ahmed-Vall

    IPC分类号： G06F9/30

    摘要： Embodiments of systems, apparatuses, and methods for broadcast arithmetic in a processor are described. For example, execution circuitry executes a decoded instruction to broadcast a data value from a least significant packed data element position of a first packed data source operand to a plurality of arithmetic circuits and for each packed data element position of a second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and stores a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand.

    Systems, Apparatuses, and Methods for Arithmetic Recurrence
    2.
    发明申请
    Systems, Apparatuses, and Methods for Arithmetic Recurrence 审中-公开

    公开(公告)号：US20180189058A1

    公开(公告)日：2018-07-05

    申请号：US15396184

    申请日：2016-12-30

    申请人： Rama Kishan V. MALLADI ,  Elmoustapha OULD-AHMED-VALL

    发明人： Rama Kishan V. MALLADI ,  Elmoustapha OULD-AHMED-VALL

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3001 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/3017

    摘要： Embodiments of systems, apparatuses, and methods for broadcast arithmetic in a processor are described. For example, execution circuitry executes a decoded instruction to broadcast a data value from a least significant packed data element position of a first packed data source operand to a plurality of arithmetic circuits and for each packed data element position of a second packed data source operand, other than a least significant packed data element position, perform the arithmetic operation defined by the instruction on a data value from that packed data element position of the second packed data source operand and all data values from packed data element positions of the second packed data source operand that are of lesser position significance to the broadcast data value from the least significant packed data element position of the first packed data source operand, and stores a result of each arithmetic operation into a packed data element position of the packed data destination operand that corresponds to a most significant packed data element position of the second packed data source operand.

    ENERGY OPTIMIZATION TECHNIQUES IN A COMPUTING SYSTEM
    4.
    发明申请
    ENERGY OPTIMIZATION TECHNIQUES IN A COMPUTING SYSTEM 有权
    计算机系统能源优化技术

    公开(公告)号：US20120089852A1

    公开(公告)日：2012-04-12

    申请号：US13018810

    申请日：2011-02-01

    申请人： Kalyan Muthukumar ,  Seshadri Harinarayanan ,  Rama Kishan V. Malladi ,  Raghavendra S. Hebbalalu ,  Mukesh Gangadhar

    发明人： Kalyan Muthukumar ,  Seshadri Harinarayanan ,  Rama Kishan V. Malladi ,  Raghavendra S. Hebbalalu ,  Mukesh Gangadhar

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126

    摘要： A computing platform may include components to determine performance loss values and energy savings values for each of the plurality of regions and/or the memory boundedness value of each of a plurality of regions within an application. The computing platform may provide a user interface for a user to provide a user input, which provides an indication of an acceptable performance loss. For the provided performance loss value, the frequency values may be determined and the processing element may be operated at the frequency values while processing each of the plurality of regions.

    摘要翻译： 计算平台可以包括用于确定多个区域中的每一个的性能损失值和能量节省值和/或应用程序内的多个区域中的每一个的存储器有界值的组件。 计算平台可以为用户提供用户界面以提供用户输入，其提供可接受的性能损失的指示。 为了提供的性能损失值，可以确定频率值，并且可以在处理多个区域中的每个区域的同时以频率值操作处理元件。