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公开(公告)号：US20170093380A1
公开(公告)日：2017-03-30
申请号：US14866469
申请日：2015-09-25
IPC分类号： H03K3/356
CPC分类号： H03K3/356104 , H03K3/0375
摘要： An apparatus is described having a latch circuit. The latch circuit includes redundant data inputs, redundant data outputs, redundant clock inputs and circuitry to self-correct a soft-error.
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公开(公告)号：US20140188968A1
公开(公告)日：2014-07-03
申请号：US13730390
申请日：2012-12-28
申请人： Himanshu KAUL , Mark A. ANDERS , Sanu K. MATHEW , Ram K. KRISHNAMURTHY , William C. HASENPLAUGH , Randy L. ALLMON , Jonathan ENOCH
发明人： Himanshu KAUL , Mark A. ANDERS , Sanu K. MATHEW , Ram K. KRISHNAMURTHY , William C. HASENPLAUGH , Randy L. ALLMON , Jonathan ENOCH
IPC分类号： G06F17/10
CPC分类号： G06F7/483 , G06F7/5443 , G06F9/30014 , G06F2207/382
摘要： Embodiments of the present invention may provide methods and circuits for energy efficient floating point multiply and/or add operations. A variable precision floating point circuit may determine the certainty of the result of a multiply-add floating point calculation in parallel with the floating-point calculation. The variable precision floating point circuit may use the certainty of the inputs in combination with information from the computation, such as, binary digits that cancel, normalization shifts, and rounding, to perform a calculation of the certainty of the result. A floating point multiplication circuit may determine whether a lowest portion of a multiplication result could affect the final result and may induce a replay of the multiplication operation when it is determined that the result could affect the final result.
摘要翻译： 本发明的实施例可以提供用于节能浮点乘法和/或添加操作的方法和电路。 可变精度浮点电路可以与浮点计算并行地确定乘法加法浮点计算的结果的确定性。 可变精度浮点电路可以结合来自计算的信息，例如取消，归一化移位和舍入的二进制数字来使用输入的确定性来执行结果的确定性的计算。 浮点乘法电路可以确定乘法结果的最低部分是否可能影响最终结果，并且当确定结果可能影响最终结果时可以引起乘法运算的重放。
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公开(公告)号：US20110095340A1
公开(公告)日：2011-04-28
申请号：US12589331
申请日：2009-10-22
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/12 , G06F2217/82 , H01L27/0207 , H01L27/092 , Y02P90/265
摘要： In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some embodiments, dummy (“off”) transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.
摘要翻译： 在一些实施例中，互补的电荷收集扩散（晶体管扩散，例如漏极或源极区）彼此靠近设置。 在一些实施例中，并入虚拟（“截止”）晶体管以使互补扩散（相同电荷类型的扩散并且具有互补数字逻辑电平）彼此更接近，否则可能是可能的，并且因此增强共模电荷收集 用于互补扩散区域。
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4.发明授权Universal CMOS single input, low swing sense amplifier without reference voltage 失效通用CMOS单输入，低摆幅读出放大器无参考电压公开(公告)号：US06414520B1
公开(公告)日：2002-07-02
申请号：US09241496
申请日：1999-02-01
IPC分类号： G01R1900
CPC分类号： G01R19/0084
摘要： A sense amplifier for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated.
摘要翻译： 用于感测数据信号的输入电压电平的读出放大器。 这种感测放大器预先对一对节点通过相应的一对放电路径进行预充电并随后放电。 这些放电路径中的每一个能够以与系统电压供应或数据信号的输入逻辑电平相关的速率执行放电操作。 由于与数据信号相关联的放电路径包括较大的电导量，所以即使在输入逻辑电平不超过系统电压电压的电压的情况下，也可以以更快的速率执行放电操作。 确定放电的哪一个更快，并且响应地产生具有与数据信号相同的极性的轨到轨输出信号。
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公开(公告)号：US08278692B2
公开(公告)日：2012-10-02
申请号：US12589331
申请日：2009-10-22
IPC分类号： H01L29/78
CPC分类号： G06F17/5045 , G06F17/5068 , G06F2217/12 , G06F2217/82 , H01L27/0207 , H01L27/092 , Y02P90/265
摘要： In some embodiments, complementary charge-collecting diffusions (transistor diffusions, e.g., drain or source areas) are disposed close to each other. In some embodiments, dummy (“off”) transistors are incorporated to bring complementary diffusions (diffusions of the same charge type and having complementary digital logic levels) closer to each other than otherwise might be possible and thus, to enhance common-mode charge collection for the complementary diffusion areas.
摘要翻译： 在一些实施例中，互补的电荷收集扩散（晶体管扩散，例如漏极或源极区）彼此靠近设置。 在一些实施例中，并入虚拟（关闭）晶体管以使互补扩散（相同电荷类型的扩散并且具有互补的数字逻辑电平）彼此更接近，否则可能是可能的，因此，为了增强共模电荷收集 互补扩散区域。
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公开(公告)号：US06653869B2
公开(公告)日：2003-11-25
申请号：US10077194
申请日：2002-02-15
IPC分类号： G01R1900
CPC分类号： G01R19/0084
摘要： A sense amplifier is provided for sensing an input voltage level of a data signal. Such a sense amplifier pre-charges, and subsequently discharges, a pair of nodes through a respective pair of discharge paths. Each of those discharge paths is capable of performing the discharge operation at a rate that is related to either a system voltage supply or an input logic level of the data signal. Because the discharge path that is associated with the data signal includes a greater amount of conductance, it can perform the discharge operation at a faster rate, even where the input logic level does not exceed the voltage of the system voltage supply. A determination is made as to which of the discharge is the faster and, responsively, a rail-to-rail output signal having the same polarity as the data signal, is generated. The input data signal is conveyed to the sense amplifier by a single wire. Also, the sense amplifier does not require a specialized reference voltage for proper operation. Rather, it uses the same voltage supply that is used to power the rest of the circuit. Accordingly, such an approach uses less area, consumes less power and has greater noise immunity.
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