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28 条记录 (耗时 0.015 秒)

    Reconfigurable SIMD vector processing system
    2.
    发明授权
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US07519646B2

    公开(公告)日：2009-04-14

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。

    Method and apparatus for treating a signal
    3.
    发明申请
    Method and apparatus for treating a signal 有权
    用于治疗信号的方法和装置

    公开(公告)号：US20090003428A1

    公开(公告)日：2009-01-01

    申请号：US11824410

    申请日：2007-06-29

    申请人： Himanshu Kaul ,  Jae-sun Seo ,  Ram K. Krishnamurthy

    发明人： Himanshu Kaul ,  Jae-sun Seo ,  Ram K. Krishnamurthy

    IPC分类号： H03K7/08

    CPC分类号： H03K5/135 ,  H03K2005/00058 ,  H03K2005/00234 ,  H03K2005/00241

    摘要： A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at least one signal a second number of the clock phases when the excursion departs toward the value in a second direction. The first number of clock phases is different from the second number of clock phases. The at least one signal effects a plurality of succeeding excursions in substantial synchrony with a clocked signal presenting succeeding clock cycles having a plurality of the clock phases in each respective clock cycle.

    摘要翻译： 一种方法包括：当偏移偏离第一方向的值时，延迟至少一个信号的偏移的第一数量的时钟相位; 以及当所述偏移在所述第二方向上偏离所述值时，将所述至少一个信号的偏移延迟到所述第二数量的时钟相位。 时钟相位的第一个数量与第二个时钟相位数不同。 所述至少一个信号与在每个相应时钟周期中具有多个时钟相位的呈现后续时钟周期的时钟信号基本同步地影响多个后续偏移。

    Encoder and decoder circuits for dynamic bus
    5.
    发明申请
    Encoder and decoder circuits for dynamic bus 有权
    用于动态总线的编码器和解码器电路

    公开(公告)号：US20050146357A1

    公开(公告)日：2005-07-07

    申请号：US10744084

    申请日：2003-12-24

    申请人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H03K19/0175 ,  H04L25/02

    CPC分类号： H04L25/0278 ,  H04L25/028

    摘要： A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.

    摘要翻译： 提供动态总线架构。 这可以包括耦合到总线线路的编码电路和耦合到总线线路的解码器电路。 编码器电路可以接收输入信号并在总线上生成编码信号。 解码器电路可以从总线接收编码信号并产生原始未编码信号。 编码器电路可以包括第一触发器电路，其基于来自总线的时钟信号来存储来自总线的先前输入信号。 此外，解码器电路可以包括具有时钟输入的第二触发器电路，以从总线接收编码信号作为时钟输入。

    Method of registering and identifying a user of a voice-controlled device
    6.
    发明申请
    Method of registering and identifying a user of a voice-controlled device 有权

    公开(公告)号：US20210012129A1

    公开(公告)日：2021-01-14

    申请号：US16508320

    申请日：2019-07-11

    申请人： Himanshu Kaul

    发明人： Himanshu Kaul

    IPC分类号： G06K9/00 ,  G10L17/22

    摘要： The present invention is related to a method of registering and identifying a user of a voice-controlled device. The method comprising: registering the user of the device, determining at least one of a facial, eye and body features of the user upon determining at least one characteristic of a voice input from the user is below a threshold level, determining an output upon comparing the determined at least one of the facial, eye and body features of the user with a prestored information associated with the user in a database and identifying the user in accordance with the determined output.

    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT
    7.
    发明申请
    COMPACT, LOW POWER ADVANCED ENCRYPTION STANDARD CIRCUIT 有权
    紧凑型低功耗高级加密标准电路

    公开(公告)号：US20150086007A1

    公开(公告)日：2015-03-26

    申请号：US14035508

    申请日：2013-09-24

    申请人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    发明人： Sanu MATHEW ,  Vikram Suresh ,  Sudhir Satpathy ,  Mark Anders ,  Himanshu Kaul ,  Ram Krishnamurthy

    IPC分类号： H04L9/30

    CPC分类号： H04L9/0631 ,  H04L2209/24

    摘要： Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption unit having a substitution box and an accumulator. The substitution box is to perform a substitution operation on one byte per clock cycle. The accumulator is to accumulate four bytes and perform a mix-column operation in four clock cycles. The encryption unit is implemented using optimum Galois Field polynomial arithmetic for minimum area.

    摘要翻译： 公开了一种用于紧凑型低功率高级加密标准电路的发明的实施例。 在一个实施例中，装置包括具有替换盒和累加器的加密单元。 替代方案是对每个时钟周期的一个字节执行替换操作。 累加器将累积四个字节，并在四个时钟周期内执行混合列操作。 加密单元使用最小区域的最优伽罗瓦域多项式运算来实现。

    Motion Estimation for Video Processing
    8.
    发明申请
    Motion Estimation for Video Processing 审中-公开
    视频处理的运动估计

    公开(公告)号：US20140105303A1

    公开(公告)日：2014-04-17

    申请号：US13649560

    申请日：2012-10-11

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Ram K. Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Ram K. Krishnamurthy

    IPC分类号： H04N7/32

    CPC分类号： H04N19/43 ,  H04N19/567

    摘要： In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.

    摘要翻译： 根据一些实施例，可以减少使用Haar，SAD和Hadamard变换的运动估计算法的复杂度。 在一些实施例中，与现有技术相比可以减少求和的数量，并且可以用比较操作来替换一些现有的求和。 在一些实施例中，为了平衡延迟和面积或能量或功率考虑，用比较代替添加。

    Reconfigurable SIMD vector processing system
    10.
    发明申请
    Reconfigurable SIMD vector processing system 有权
    可重构SIMD矢量处理系统

    公开(公告)号：US20080104164A1

    公开(公告)日：2008-05-01

    申请号：US11586810

    申请日：2006-10-26

    申请人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    发明人： Himanshu Kaul ,  Mark A. Anders ,  Sanu Mathew ,  Ram Krishnamurthy

    IPC分类号： G06F7/52

    CPC分类号： G06F7/5324 ,  G06F2207/3828

    摘要： A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.

    摘要翻译： 系统可以包括用于以冗余格式输出M 2N位产品的M N位×N位乘法器，用于接收M 2N位乘积并基于M 2N产生冗余格式的MN位乘积的压缩器 以及用于接收M 2N位乘积和MN位乘积的加法器块，从M 2N位乘积或MN位乘积中选择一个，并将所选择的一个M 2N 位产品或MN位产品为非冗余格式。