公开(公告)号：US5745790A

公开(公告)日：1998-04-28

申请号：US812445

申请日：1997-03-06

申请人： Rasoul M. Oskouy

发明人： Rasoul M. Oskouy

IPC分类号： G06F13/38 ,  G06F5/06 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04Q3/00 ,  H04Q3/545 ,  G06F9/28 ,  G06F13/14

CPC分类号： H04L29/06 ,  G06F5/06 ,  H04L69/32

摘要： A method and apparatus of reporting the status of data transfer between software and hardware in a computer system is disclosed. Software provides empty descriptors to the hardware for posting completion updates of transfers. More particularly, the software provides the number of the last available descriptor to a first storage field in a storage location which is accessible to the hardware. The hardware accounts for the number of the descriptors it has used for reporting completion updates by posting the number of used descriptors to a second storage field in the storage location. To determine if more descriptors are available, the hardware compares the contents of the first storage field to that of the second storage field. If the contents of the first and second storage fields are equal, the hardware has reached the last descriptor in the completion ring. If the fields are not equal, one or more descriptors are available for the hardware to use.

摘要翻译： 公开了一种在计算机系统中报告软件和硬件之间的数据传送状态的方法和装置。 软件为硬件提供空描述符，用于发布传输完成更新。 更具体地，软件将最后可用描述符的数量提供给硬件可访问的存储位置中的第一存储字段。 硬件通过将已使用的描述符数量发布到存储位置中的第二个存储字段来计算其用于报告完成更新的描述符数。 为了确定更多描述符是否可用，硬件将第一个存储字段的内容与第二个存储字段的内容进行比较。 如果第一和第二存储字段的内容相等，则硬件已经到达完成环中的最后一个描述符。 如果字段不相等，则一个或多个描述符可供硬件使用。

公开(公告)号：US5680401A

公开(公告)日：1997-10-21

申请号：US549538

申请日：1995-10-27

申请人： Andre Gayton ,  Rasoul M. Oskouy

发明人： Andre Gayton ,  Rasoul M. Oskouy

IPC分类号： H04Q3/00 ,  H04L12/56 ,  H04Q11/04 ,  H04J3/26

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652

摘要： A network interface card (NIC) is provided with a transmit unload block for asynchronously segmenting packet data into ATM cells for packets of multiple channels. The transmit unload block comprises a cellification block and a cellification and DMA scheduler. The cellification block is used to perform the actual cellification of the packet data into ATM cells, one ATM cell at a time, and management of the packet control data associated with the ATM cell's packet as well as management of the buffer control data associated with the ATM cell's channel. The construction of the current ATM cell is overlapped with the management of the packet and buffer control data associated with the immediately preceding ATM cell. The cellification and DMA scheduler is used to control the operation of the cellification block. The cellification and DMA scheduler is also used to schedule DMAs to obtain additional packet data for the channels.

摘要翻译： 网络接口卡（NIC）具有发送卸载块，用于将分组数据异步地分组到多个信道的分组的ATM信元中。 发送卸载块包括蜂窝化块和蜂窝化和DMA调度器。 单元化块用于一次将ATM信元，ATM信元，ATM信元相关联的分组控制数据的管理与ATM信元的实际信元化，以及与该ATM信元相关联的缓冲器控制数据的管理 ATM信元的通道。 当前ATM信元的结构与前一ATM信元相关联的数据包和缓冲器控制数据的管理重叠。 细胞化和DMA调度器用于控制细胞化块的操作。 细胞化和DMA调度器也用于调度DMA以获得用于信道的附加分组数据。

公开(公告)号：US5633870A

公开(公告)日：1997-05-27

申请号：US499197

申请日：1995-07-07

申请人： Andre J. Gaytan ,  Rasoul M. Oskouy

发明人： Andre J. Gaytan ,  Rasoul M. Oskouy

IPC分类号： G06F13/00 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04Q3/00 ,  H04Q11/04 ,  H04J3/16

CPC分类号： H04Q11/0478 ,  H04L29/06 ,  H04L49/90 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L69/324

摘要： A method and network interface for controlling the flow of data between a and an ATM network is provided. The network interface resides on an ATM interface and includes a state machine for each channel supported by the ATM interface. The state machine moves from state to state based on the contents of a local buffer, indications that data for the channel is ready to be transferred from the host computer to the local buffer, and the status of operations that transfer data for the channel from the host computer to the local buffer. The ATM interface includes a DMA unit and a segmentation unit that operate responsive to the states of the various state machines to avoid inefficient transfer operations. Specifically, the DMA unit does not attempt to move data for a channel from the host computer to the local buffer if the state of the state machine for the channel indicates that (1) there is no more data in the host computer for the channel or (2) there is no more room in the local buffer to receive data for the channel from the host computer. The segmentation unit does not attempt to transmit cells for a channel when the state of the state machine for the channel indicates that the local buffer does not contain enough data for the channel to construct a cell for the channel.

摘要翻译： 提供了一种用于控制ATM网络之间的数据流的方法和网络接口。 网络接口驻留在ATM接口上，并包括ATM接口支持的每个通道的状态机。 状态机基于本地缓冲器的内容从状态移动到状态，指示信道的数据准备好从主计算机传送到本地缓冲器，以及将信道的数据从 主机到本地缓冲区。 ATM接口包括DMA单元和分段单元，其响应于各种状态机的状态而操作以避免低效的传输操作。 具体来说，如果通道的状态机的状态表明（1）在主计算机中没有更多的数据，则DMA单元不会尝试将数据从主机移动到本地缓冲器，或者 （2）本地缓冲区没有更多的空间从主机接收频道的数据。 当信道的状态机的状态指示本地缓冲器不包含用于构建信道的小区的信道的足够数据时，分段单元不尝试发送信道的小区。

公开(公告)号：US07571168B2

公开(公告)日：2009-08-04

申请号：US11459909

申请日：2006-07-25

申请人： Cameron Bahar ,  Joseph Hopfield ,  Naveen Nalam ,  David B. Zafman ,  Rasoul M. Oskouy

发明人： Cameron Bahar ,  Joseph Hopfield ,  Naveen Nalam ,  David B. Zafman ,  Rasoul M. Oskouy

IPC分类号： G06F17/30 ,  G06F12/00

CPC分类号： G06F17/30212 ,  G06F9/5011 ,  G06F9/5016 ,  G06F2209/508 ,  H04L29/12207 ,  H04L61/20 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1017 ,  H04L67/1029 ,  H04L67/1095 ,  H04L67/1097 ,  H04L67/2814 ,  Y10S707/99931 ,  Y10S707/99952 ,  Y10S707/99953

摘要： File system independent techniques and mechanisms for replicating files on multiple devices are provided, migrating files from one device to another (for purposes of reliability, increased bandwidth, load balancing, capacity expansion, or reduced cost), and propagating updates from a master copy to remote replicas. The mechanisms involve work queues and asynchronous file migration daemons that operate independently from and in parallel with the primary client-server and network protocol to on-disk storage data paths.

摘要翻译： 提供了用于在多个设备上复制文件的文件系统独立技术和机制，将文件从一个设备迁移到另一个设备（为了可靠性，增加的带宽，负载平衡，容量扩展或降低的成本），并将更新从主副本传播到 远程副本。 这些机制涉及与主客户机 - 服务器和网络协议独立于并行运行到磁盘存储数据路径的工作队列和异步文件迁移守护程序。

公开(公告)号：US5859856A

公开(公告)日：1999-01-12

申请号：US958851

申请日：1997-10-27

申请人： Rasoul M. Oskouy ,  Denny Gentry

发明人： Rasoul M. Oskouy ,  Denny Gentry

IPC分类号： G06F13/00 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/28

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5658 ,  H04L2012/5679 ,  H04L2012/5681 ,  Y10S370/902

摘要： A number of storage units and a number of state machines are provided to reorder interleaved ATM data cells for a number of channels incoming to a networked host computer. The storage units store the incoming ATM data cells, a number of data structures tracking the stored ATM data cells for the channels and the free resources, and an unload schedule queue. The state machines load and unload the incoming ATM data cells, and update the tracking data structures and schedule queue accordingly.

摘要翻译： 提供了多个存储单元和多个状态机以对交织的ATM数据单元重新排序输入到联网主计算机的多个通道。 存储单元存储输入的ATM数据单元，跟踪用于信道和可用资源的存储的ATM数据单元的多个数据结构以及卸载调度队列。 状态机加载和卸载传入的ATM数据单元，并相应地更新跟踪数据结构和调度队列。

公开(公告)号：US5778180A

公开(公告)日：1998-07-07

申请号：US554608

申请日：1995-11-06

申请人： Denton E. Gentry ,  Rasoul M. Oskouy

发明人： Denton E. Gentry ,  Rasoul M. Oskouy

IPC分类号： G06F13/00 ,  G06F13/12 ,  H04L12/56 ,  H04L29/10 ,  H04Q11/04 ,  G06F13/14

CPC分类号： H04Q11/0478 ,  G06F13/128 ,  H04L2012/5616 ,  H04L2012/5652 ,  H04L2012/5681

摘要： A method and an apparatus for reducing data copying overhead associated with protected memory operating systems. In an ATM (Asynchronous Transfer Method) network, the present invention's NIC (network interface circuit) demultiplexes the information in the header of the incoming packet and routes the packet directly to its final destination using the present invention's concept of targeted buffer rings. Thus, instead of having the packet be DMA'd to a buffer in a descriptor ring in the kernel, it may be routed directly to the buffer ring of the destination process.

摘要翻译： 一种用于减少与受保护的存储器操作系统相关联的数据复制开销的方法和装置。 在ATM（异步传输方法）网络中，本发明的NIC（网络接口电路）使用本发明的目标缓冲环的概念对输入分组的报头中的信息进行解复用，并将分组直接路由到其最终目的地。 因此，代替将数据包DMA到内核中的描述符环中的缓冲区，它可以直接路由到目的地进程的缓冲环。

公开(公告)号：US5758089A

公开(公告)日：1998-05-26

申请号：US552342

申请日：1995-11-02

申请人： Denny E. Gentry ,  Rasoul M. Oskouy

发明人： Denny E. Gentry ,  Rasoul M. Oskouy

IPC分类号： G06F13/00 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  G06F13/38 ,  H04J3/24

CPC分类号： H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5619 ,  H04L2012/5681

摘要： A network interface circuit (NIC) is provided with logic for maintaining various control pointers and at least one control counter for controlling burst transferring of buffered ATM cells to its host computer system in a non-cellboundary-aligned block manner, distinguishing the ATM packet header from the ATM data most of the time, except for a number of predetermined exceptions. More specifically, ATM packet headers and ATM data are to be burst transferred to separate header and data buffers on the host computer system, except for short and atypical packets, in fixed size blocks, where the block size is complementary to the interface bus, but not necessarily aligned with the ATM cell boundaries. For the short and atypical packets, both the header and data are to be burst transferred into the header buffer instead. The logic employs a two phase approach to determining the appropriate updates to the relevant control pointers and at least one control counter after each burst transfer of header/data to the header/data buffer. In one embodiment, the logic is provided to the lookahead state machine of an unload block, which is part of the receive block of a system and ATM layer core of the NIC.

摘要翻译： 网络接口电路（NIC）具有用于维护各种控制指针和至少一个控制计数器的逻辑，用于以非小区边界对准的块方式控制缓冲的ATM信元到其主计算机系统的突发传送，区分ATM分组报头 来自ATM数据的大部分时间，除了一些预定的例外。 更具体地说，除了块大小与接口总线互补的固定大小块之外，ATM分组报头和ATM数据将被突发传送到主计算机系统上的单独的报头和数据缓冲区，除了短和非典型的分组之外，但是 不一定与ATM信元边界对齐。 对于短和非典型数据包，头部和数据都将被突发传输到标头缓冲区中。 该逻辑采用两相方法来确定对标题/数据缓冲器的每个突发传送头/数据之后相关控制指针和至少一个控制计数器的适当更新。 在一个实施例中，逻辑被提供给卸载块的前瞻状态机，卸载块是NIC的系统和ATM层核心的接收块的一部分。

公开(公告)号：US07599941B2

公开(公告)日：2009-10-06

申请号：US11459905

申请日：2006-07-25

申请人： Cameron Bahar ,  Joseph Hopfield ,  Naveen Nalam ,  David B. Zafman ,  Rasoul M. Oskouy

发明人： Cameron Bahar ,  Joseph Hopfield ,  Naveen Nalam ,  David B. Zafman ,  Rasoul M. Oskouy

IPC分类号： G06F17/30 ,  G06F12/00

CPC分类号： G06F17/30212 ,  G06F9/5011 ,  G06F9/5016 ,  G06F2209/508 ,  H04L29/12207 ,  H04L61/20 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/1017 ,  H04L67/1029 ,  H04L67/1095 ,  H04L67/1097 ,  H04L67/2814 ,  Y10S707/99931 ,  Y10S707/99952 ,  Y10S707/99953

摘要： A storage system includes a plurality of storage servers that store a plurality of files, a monitor module, and a redirector module. The monitor module monitors usage information associated with the plurality of storage servers. The redirector module determines, based on the monitored usage information, a storage server in the plurality of storage servers to service a session from a client. The redirector module then instructs the client to establish the session with the determined storage server.

摘要翻译： 存储系统包括存储多个文件的多个存储服务器，监视器模块和重定向器模块。 监视器模块监视与多个存储服务器相关联的使用信息。 重定向器模块基于所监视的使用情况确定多个存储服务器中的存储服务器，以从客户端服务会话。 重定向器模块然后指示客户端与确定的存储服务器建立会话。

公开(公告)号：US5875352A

公开(公告)日：1999-02-23

申请号：US553041

申请日：1995-11-03

申请人： Denton E. Gentry ,  Rasoul M. Oskouy

发明人： Denton E. Gentry ,  Rasoul M. Oskouy

IPC分类号： G06F13/12 ,  G06F12/12 ,  G06F13/10 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F12/123 ,  G06F13/10

摘要： An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports multiple virtual channels in a high speed network interface. When an access to a particular channel state is performed, e.g., by a host processor or the DMA device, the cache is first accessed and if the state information is not located currently in the cache, external memory is read and the state information is written to the cache. As the cache does not store all the states stored in external memory, replacement algorithms are utilize to determine which channel state information to remove from the cache in order to provide room to store a recently accessed channel. A doubly linked list is used to track the most recently used channel. As cached channel information is accessed, the corresponding entry is moved to the top of the list. The doubly linked list provides a rapid apparatus and method for updating pointers to the cache. Top and bottom pointers are maintained, pointing to the most recently used and least recently used channels. When a channel is used, it moved to the top of the list. When channel data is moved from external memory to the cache, the bottom pointer points to the channel data to be removed from the cache.

摘要翻译： 使用片上高速缓冲存储器来为频繁使用的信道状态信息提供高速接入机制，用于在高速网络接口中支持多个虚拟信道的DMA设备的操作。 当执行对特定信道状态的访问时，例如由主处理器或DMA设备执行时，首先访问高速缓存，并且如果状态信息当前不位于高速缓存中，则读取外部存储器并写入状态信息 到缓存。 由于高速缓存不存储存储在外部存储器中的所有状态，因此利用替换算法来确定要从高速缓存中移除哪个信道状态信息，以便提供存储最近访问的信道的空间。 双向链表用于跟踪最近使用的频道。 随着缓存的频道信息被访问，相应的条目被移动到列表的顶部。 双向链表提供了一种用于更新指向缓存的指针的快速装置和方法。 保持顶部和底部指针，指向最近使用的和最近最少使用的通道。 当使用频道时，它会移动到列表的顶部。 当通道数据从外部存储器移动到高速缓存时，底部指针指向要从高速缓存中移除的通道数据。

公开(公告)号：US5745684A

公开(公告)日：1998-04-28

申请号：US554074

申请日：1995-11-06

申请人： Rasoul M. Oskouy ,  Louise Yeung

发明人： Rasoul M. Oskouy ,  Louise Yeung

IPC分类号： G06F13/00 ,  G06F13/12 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/00

CPC分类号： G06F13/128 ,  H04Q11/0478 ,  H04L2012/5616 ,  H04L2012/5652

摘要： A generic Input/Output interface between an IO block and a System and ATM Layer Core on a network interface circuit is provided. The GIO interface includes parallel DMA read and write control handshake signal lines; parallel DMA read and write data handshake signal lines which operate independently from the read and write control handshake signal lines; parallel DMA read and write data signal lines; and a single clock signal line. GIO interface facilitates maximum utilization of the IO bandwidth, and allows several requests to be queued across the GIO interface at the same time, in each read and write direction. In addition, the GIO interface utilizes a fixed clock for driving the transmit and receive data path. By thus referencing all transactions to a clock driving the Core, the Core remains unchanged for different embodiments of the network interface circuit which interface to different host computer systems and busses.

摘要翻译： 提供了IO块与网络接口电路上的系统和ATM层核心之间的通用输入/输出接口。 GIO接口包括并行DMA读写控制握手信号线; 并行DMA读写数据握手信号线，独立于读写控制握手信号线工作; 并行DMA读写数据信号线; 和单个时钟信号线。 GIO接口有助于最大限度地利用IO带宽，并允许在每个读取和写入方向的同时，跨GIO接口排队多个请求。 此外，GIO接口使用固定时钟来驱动发送和接收数据路径。 通过这样将所有事务引用到驱动核心的时钟，对于与不同主机计算机系统和总线接口的网络接口电路的不同实施例，核心保持不变。