公开(公告)号：US06324613B1

公开(公告)日：2001-11-27

申请号：US09477593

申请日：2000-01-04

申请人： Raul A. Aguilar ,  Kevin Joseph Lynch ,  James Thomas Clee ,  James Edward Guziak

发明人： Raul A. Aguilar ,  Kevin Joseph Lynch ,  James Thomas Clee ,  James Edward Guziak

IPC分类号： G06F1314

CPC分类号： G06F9/4411 ,  H04L49/25 ,  H04L49/351

摘要： An apparatus and method which provide increased data flow through a compute platform by optimizing data flow between an external device and the internal circuitry without the need for user intervention. A port router is provided which includes a controller switch, a port switch, and one or more connections between the controller switch and the port switch. The controller switch, the port switch and the one or more connections are adapted to provide dynamic re-routing of connections between the port switch inputs and the controller switch outputs. A method is also provided for dynamically routing ports to internal circuitry of a compute platform. The method includes providing a configurable switching circuit, querying the configurable switching circuit to determine a default topology, computing an optimized topology upon the occurrence of a change of the data flow through the configurable switching circuit, suspending operation and effecting re-routing between the interface ports and the internal circuitry based on the optimized topology, and resuming IO operations through the configurable switching circuit. The method and apparatus may be applied to personal computer systems, information appliances, set-top boxes, cable modems, game consoles, smart appliances, handheld computers, palm-sized computers, embedded control systems, workstations, servers and the like.

摘要翻译： 一种通过优化外部设备和内部电路之间的数据流而不需要用户干预通过计算平台提供增加的数据流的装置和方法。 提供了一个端口路由器，其中包括控制器交换机，端口交换机以及控制器交换机和端口交换机之间的一个或多个连接。 控制器开关，端口开关和一个或多个连接适于提供端口开关输入和控制器开关输出之间的连接的动态重新路由。 还提供了一种用于将端口动态地路由到计算平台的内部电路的方法。 该方法包括提供可配置的切换电路，查询可配置切换电路以确定默认拓扑，在发生通过可配置切换电路的数据流的改变时计算优化的拓扑，暂停操作并在接口之间实现重新路由 端口和基于优化拓扑的内部电路，并通过可配置的开关电路恢复IO操作。 该方法和装置可以应用于个人计算机系统，信息设备，机顶盒，电缆调制解调器，游戏机，智能家电，手持式计算机，掌上型计算机，嵌入式控制系统，工作站，服务器等。

公开(公告)号：US5473556A

公开(公告)日：1995-12-05

申请号：US117959

申请日：1993-09-08

申请人： Raul A. Aguilar ,  Jeffrey L. Miller

发明人： Raul A. Aguilar ,  Jeffrey L. Miller

IPC分类号： G06F7/76 ,  G06F17/14 ,  G06F15/00

CPC分类号： G06F7/768 ,  G06F17/142

摘要： A digit reversing system is disclosed for handling mixed radix FFT operations with arbitrary arrangements of radices. In a first step, all bits in an integer field of size log.sub.2 N are position reversed. In a second step, subfields of the output produced in the first step are individually unreversed at the local level to produce unreversed digits. The output is used for appropriately arranging input terms applied to a mixed-radix multi-stage Fast Fourier Transform (FFT) process.

摘要翻译： 公开了一种数字反转系统，用于处理具有任意排列的阵列的混合基数FFT运算。 在第一步中，大小为log2N的整数字段中的所有位都位置相反。 在第二步骤中，在第一步骤中产生的输出的子场在本地级单独未被转换，以产生未被转换的数字。 该输出用于适当地排列应用于混合式多阶段快速傅里叶变换（FFT）处理的输入项。

公开(公告)号：US06199137B1

公开(公告)日：2001-03-06

申请号：US09477591

申请日：2000-01-04

申请人： Raul A. Aguilar ,  Kevin Joseph Lynch ,  James Thomas Clee ,  James Edward Guziak ,  Farrukh Amjad Latif

发明人： Raul A. Aguilar ,  Kevin Joseph Lynch ,  James Thomas Clee ,  James Edward Guziak ,  Farrukh Amjad Latif

IPC分类号： G06F1340

CPC分类号： G06F9/4411 ,  H04L49/25 ,  H04L49/351

摘要： An IO controller device and method for controlling data flow, the method including determining a desired configuration for the IO controller, reprogramming the IO controller to allow for processing of one or more descriptor lists, modifying the configuration of the IO controller to reflect the addition or deletion of one or more virtual controllers, re-enumerating the IO controller, and processing a descriptor list for each of the IO controller and the one or more virtual controllers. The integrated circuit device for use as an IO controller includes a system bus interface, a programmable list processor and a port router. The integrated circuit device is adapted for reconfiguration to add or delete one or more virtual controllers. The virtual controllers provide substantially the full bandwidth supported by the integrated circuit device. The IO controller device and apparatus may be applied to personal computer systems, information appliances, set-top boxes, cable modems, game consoles, smart appliances, handheld computers, palm-sized computers, embedded control systems, workstations, servers and the like.

摘要翻译： 一种用于控制数据流的IO控制器设备和方法，所述方法包括确定IO控制器的期望配置，重新编程IO控制器以允许处理一个或多个描述符列表，修改IO控制器的配置以反映添加或 删除一个或多个虚拟控制器，重新列举IO控制器，以及处理每个IO控制器和一个或多个虚拟控制器的描述符列表。 用作IO控制器的集成电路装置包括系统总线接口，可编程列表处理器和端口路由器。 集成电路设备适于重新配置以添加或删除一个或多个虚拟控制器。 虚拟控制器基本上提供集成电路设备支持的全部带宽。 IO控制器设备和设备可以应用于个人计算机系统，信息设备，机顶盒，电缆调制解调器，游戏机，智能家电，手持计算机，掌上型计算机，嵌入式控制系统，工作站，服务器等。

公开(公告)号：US5029079A

公开(公告)日：1991-07-02

申请号：US228611

申请日：1988-08-04

申请人： Surendar S. Magar ,  Gerry C. Lui Kuo ,  Raul A. Aguilar ,  Michael E. Fleming

发明人： Surendar S. Magar ,  Gerry C. Lui Kuo ,  Raul A. Aguilar ,  Michael E. Fleming

IPC分类号： G06F17/10 ,  G06F17/14

CPC分类号： G06F17/142 ,  G06F17/10

摘要： A control apparatus for use with a digital signal processing device and associated memory units is described. The control apparatus determines, along with the electrical configuration of the digital signal processing device and associated memory units, the application of members of a signal array to be processed and the removal of the members of a processed signal array from the digital signal processing device. The control apparatus controls the location of data exchanged between the digital signal processing device and the associated memory units. The control apparatus permits the digital signal processing device and associated memory units to operate in a normal mode where a predetermined processing operation is performed on the members of a signal array, a recursive mode where a series of operations are performed on a signal array by a single digital signal processing unit, and a sequential mode where a series of processing operations are performed on a signal array using a by plurality of digital signal processing units coupled in a series arrangement. The control apparatus has provision for automatic accommodation of predetermined latency in the signal member path, resulting from pipelined computation and from pipelined memory accesses, as well as accommodating preselected signal array sizes and preselected signal array overlap.

摘要翻译： 描述了一种与数字信号处理装置和相关联的存储器单元一起使用的控制装置。 控制装置连同数字信号处理装置和相关联的存储器单元的电气配置一起确定要处理的信号阵列的构件的应用以及从数字信号处理装置移除处理的信号阵列的构件。 控制装置控制在数字信号处理装置和相关联的存储器单元之间交换的数据的位置。 控制装置允许数字信号处理装置和相关联的存储器单元在正常模式下操作，其中对信号阵列的成员执行预定的处理操作，递归模式，其中对信号阵列执行一系列操作， 单数字信号处理单元，以及使用以串联方式耦合的多个数字信号处理单元对信号阵列执行一系列处理操作的顺序模式。 控制装置具有用于自动调节信号构件路径中预定等待时间的结果，这是由流水线计算和流水线存储器访问产生的，以及容纳预选信号阵列大小和预选信号阵列重叠。