公开(公告)号：US06483342B2

公开(公告)日：2002-11-19

申请号：US09864277

申请日：2001-05-25

申请人： Barry K. Britton ,  Ravikumar Charath ,  Zheng Chen ,  James F. Hoff ,  Cort D. Lansenderfer ,  Don McCarley ,  Richard G. Stuby, Jr. ,  Ju-Yuan D. Yang

发明人： Barry K. Britton ,  Ravikumar Charath ,  Zheng Chen ,  James F. Hoff ,  Cort D. Lansenderfer ,  Don McCarley ,  Richard G. Stuby, Jr. ,  Ju-Yuan D. Yang

IPC分类号： H03K19177

CPC分类号： G06F1/10 ,  H03K5/13 ,  H03K5/133 ,  H03K19/017581 ,  H03K19/17732 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H03K19/17788 ,  H03K19/17792 ,  H03L7/081 ,  H03L7/0996

摘要： An embedded system bus is woven between a plurality of embedded master elements and at least one slave element within the FPGA device, and provides an external processor interface allowing direct access to any of the plurality of embedded slave elements. Using the embedded system bus, any of a plurality of masters may be allowed to program an embedded element, e.g., embedded FPGA logic, whereas conventional FPGAs allowed only a single master (e.g., a processor) to program the embedded FPGA logic. The embedded system bus is a group of signals, typically data, address and control, that connects system elements together and provides a basic protocol for the flow of data. The embedded system bus allows for control, configuration and status determination of the FPGA device. The embedded system bus is preferably a dedicated function available at all times for arbitrated access to allow communication between the various embedded system components.

摘要翻译： 嵌入式系统总线在多个嵌入式主元件和FPGA器件内的至少一个从属元件之间编织，并提供允许直接访问多个嵌入式从属元件中的任一个的外部处理器接口。 使用嵌入式系统总线，可以允许多个主机中的任何一个主机对嵌入式元件（例如，嵌入式FPGA逻辑）进行编程，而常规FPGA只允许单个主机（例如，处理器）编程嵌入式FPGA逻辑。 嵌入式系统总线是一组信号，通常是数据，地址和控制，将系统元件连接在一起，并为数据流提供基本协议。 嵌入式系统总线允许FPGA器件的控制，配置和状态确定。 嵌入式系统总线优选地是可随时用于仲裁访问的专用功能，以允许各种嵌入式系统组件之间的通信。

公开(公告)号：US20060273941A1

公开(公告)日：2006-12-07

申请号：US11143370

申请日：2005-06-02

申请人： Ravikumar Charath ,  Vladimir Sindalovsky ,  Lane Smith

发明人： Ravikumar Charath ,  Vladimir Sindalovsky ,  Lane Smith

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H04J3/0632 ,  H04J3/0685

摘要： The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments determine whether a data alignment signal has been written, for each data channel of the plurality of data channels, such as a comma character. When a data alignment signal has been written in a data channel of the plurality of data channels, the embodiments determine a corresponding channel location of the data alignment signal for each data channel having the data alignment signal. When each data channel of the plurality of data channels has the data alignment signal, and when the data alignment signal is to be read on a next read cycle in at least one data channel, the various embodiments move a corresponding read pointer for each data channel of the plurality of data channels to the corresponding channel location of the data alignment signal. The data alignment signal is then read in all channels during the next read cycle, followed by subsequent reading of deskewed or otherwise synchronized data, such as for conversion of parallel data into serial data for subsequent data transmission.