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    Innovative method of correlated double sample (CDS) circuit testing
    1.
    发明授权
    Innovative method of correlated double sample (CDS) circuit testing 有权
    相关双样本（CDS）电路测试的创新方法

    公开(公告)号：US07298304B2

    公开(公告)日：2007-11-20

    申请号：US10294163

    申请日：2002-11-14

    Applicant: Ganesh Kamath ,  Ravishankar S. Ayyagari

    Inventor： Ganesh Kamath ,  Ravishankar S. Ayyagari

    IPC: H03M1/10

    CPC classification number: H04N17/002

    Abstract: The present invention comprises a test set-up (20) and method of testing a correlated double sampling circuit (CDS) (24) by using a sinusoidal test signal (22) for measuring linearity. The present invention generates a sinusoidal signal with two accurate and known levels at two different time points, as an input to the CDS. The cosinusoidal output of the CDS is then processed using an ADC (60) and processor (62) to check the functionality and linearity of the CDS circuit under test.

    Abstract translation: 本发明包括测试装置（20）以及通过使用用于测量线性度的正弦测试信号（22）来测试相关双重采样电路（CDS）（24）的方法。 本发明在两个不同的时间点产生具有两个准确和已知电平的正弦信号，作为CDS的输入。 然后使用ADC（60）和处理器（62）处理CDS的cosinusoidal输出，以检查被测CDS电路的功能和线性。

    Low power comparator comparing differential signals
    3.
    发明授权
    Low power comparator comparing differential signals 有权
    低功率比较器比较差分信号

    公开(公告)号：US06489813B2

    公开(公告)日：2002-12-03

    申请号：US09794765

    申请日：2001-02-26

    Applicant: Suhas R. Kulhalli ,  Ravishankar S. Ayyagari

    Inventor： Suhas R. Kulhalli ,  Ravishankar S. Ayyagari

    IPC: H03K5153

    CPC classification number: H03K5/24

    Abstract: A comparator comparing a differential input signal (represented by INM and INP single ended signals) with a differential reference signal (REFP and REFM) to generate a comparison result. The result may be amplified by a desired high amplification factor while consuming minimal electrical power. The comparator may contain two regenerative latches, with each latch containing two terminals. The INM, INP, REFP, and REFM are provided on the four terminals via respective switches. The first and second terminals of the first regenerative latch may respectively be connected to the first and second terminals of the second regenerative latch, with a switch in the path of each connection. The switches may be operated and the regenerative latches may be enabled for a short duration, to generate an amplified comparison result.

    Abstract translation: 将差分输入信号（由INM和INP单端信号表示）与差分参考信号（REFP和REFM）进行比较以产生比较结果的比较器。 结果可以通过期望的高放大因子放大，同时消耗最小的电功率。 比较器可以包含两个再生锁存器，每个锁存器包含两个端子。 通过相应的开关在四个端子上提供INM，INP，REFP和REFM。 第一再生锁存器的第一和第二端子可以分别连接到第二再生锁存器的第一和第二端子，并且每个连接的路径中都有一个开关。 可以操作开关并且可以在短时间内使能再生锁存器，以产生放大的比较结果。

    Switch for handling terminal voltages exceeding control voltage
    5.
    发明授权
    Switch for handling terminal voltages exceeding control voltage 有权
    用于处理端子电压超过控制电压的开关

    公开(公告)号：US07498862B2

    公开(公告)日：2009-03-03

    申请号：US11160879

    申请日：2005-07-14

    Applicant: Ravishankar S. Ayyagari

    Inventor： Ravishankar S. Ayyagari

    IPC: H03K17/00

    CPC classification number: H03K17/102 ,  H03K17/6871 ,  Y10T307/964

    Abstract: A switch provided between a first terminal and a second terminal with a varying cross terminal voltage. The switch contains two transistors, with the source terminal of the first transistor being coupled to the first terminal and a drain terminal of the second transistor being coupled to the second terminal. The gate terminal of the first transistor is coupled to the first terminal, the gate terminal of the second transistor is coupled to the second terminal, and the drain terminal of the first transistor is coupled to the source terminal of the second transistor. Due to such a topology, the cross-terminal voltage across the first and second terminals can be substantially higher than the voltage of the control signal indicating whether the switch is to be in on or off state.

    Abstract translation: 设置在具有变化的交叉端电压的第一端子和第二端子之间的开关。 开关包含两个晶体管，其中第一晶体管的源极端子耦合到第一端子，并且第二晶体管的漏极端子耦合到第二端子。 第一晶体管的栅极端子耦合到第一端子，第二晶体管的栅极端子耦合到第二端子，第一晶体管的漏极端子耦合到第二晶体管的源极端子。 由于这样的拓扑结构，跨越第一和第二端子的跨端电压可以显着地高于控制信号的电压，指示开关是开或关状态。

    Bandwidth limited sampling circuit of high linearity
    6.
    发明授权
    Bandwidth limited sampling circuit of high linearity 有权
    带宽限制采样电路线性度高

    公开(公告)号：US07015850B2

    公开(公告)日：2006-03-21

    申请号：US10710620

    申请日：2004-07-26

    Applicant: Ravishankar S. Ayyagari ,  Visvesvaraya A. Pentakota

    Inventor： Ravishankar S. Ayyagari ,  Visvesvaraya A. Pentakota

    IPC: H03M1/12

    CPC classification number: H04N5/378 ,  G11C27/026

    Abstract: A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using a second circuit portion to sample the bandwidth limited input signal. The first circuit portion and the second circuit portion may be implemented using separate components. In an alternative embodiment, bandwidth limiting is implemented by taking a difference of a sampled input signal from a sampled high frequency components of the input signal.

    Abstract translation: 可以通过使用第一电路部分来限制输入信号的带宽并且使用第二电路部分对带宽限制的输入信号进行采样来实现高线性的带宽限制采样电路。 第一电路部分和第二电路部分可以使用单独的部件来实现。 在替代实施例中，通过从输入信号的采样高频分量中取样输入信号的差异来实现带宽限制。

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