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公开(公告)号：US07579975B2
公开(公告)日：2009-08-25
申请号：US11954209
申请日：2007-12-11
Applicant: Sandeep Mallya Perdoor , Abhaya Kumar , Shakti Shankar Rath
Inventor： Sandeep Mallya Perdoor , Abhaya Kumar , Shakti Shankar Rath
IPC: H03M1/34
CPC classification number: H03M1/0682 , H03M1/168 , H03M1/361
Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.
Abstract translation: 流水线ADC处理差分信号中的残留块包含多对电容。 在保持工作期间，一对电容器连接到正参考电压，如果输入信号超过相应的阈值电压，另一个电容器连接到负参考电压。 当输入信号不超过相应的阈值电压时，该对的两个电容均连接到正或负参考电压。 结果，可以消除对共模参考电压的需要，并且可以以较小的面积来实现残留块。
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2.发明申请Residue Signal Generator Architecture With Reduced Number Of Switches For Use In A Pipeline Adc Processing Differential Signals 有权残留信号发生器架构，减少开关数量用于管道Adc处理差分信号公开(公告)号：US20090146855A1
公开(公告)日：2009-06-11
申请号：US11954209
申请日：2007-12-11
Applicant: Sandeep Mallya Perdoor , Abhaya Kumar , Shakti Shankar Rath
Inventor： Sandeep Mallya Perdoor , Abhaya Kumar , Shakti Shankar Rath
CPC classification number: H03M1/0682 , H03M1/168 , H03M1/361
Abstract: A residue block in a stage of a pipeline ADC processing differential signals contains multiple pairs of capacitors. During a hold phase of operation, one capacitor of a pair is connected to a positive reference voltage, and the other capacitor is connected to a negative reference voltage if the input signal exceeds a corresponding threshold voltage. When the input signal does not exceed the corresponding threshold voltage, both capacitors of the pair are connected either to the positive or the negative reference voltage. As a result, the need for a common mode reference voltage may be eliminated, and the residue block can be implemented with a smaller area.
Abstract translation: 流水线ADC处理差分信号中的残留块包含多对电容。 在保持工作期间，一对电容器连接到正参考电压，如果输入信号超过相应的阈值电压，另一个电容器连接到负参考电压。 当输入信号不超过相应的阈值电压时，该对的两个电容均连接到正或负参考电压。 结果，可以消除对共模参考电压的需要，并且可以以较小的面积来实现残留块。
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公开(公告)号：US07088273B1
公开(公告)日：2006-08-08
申请号：US11160855
申请日：2005-07-13
IPC: H03M1/10
CPC classification number: H03M1/0863 , H03M1/167
Abstract: A switched capacitor environment in which a feedback capacitor of a stage is flipped to be used as a sampling capacitor of the next stage. Due to such use of the feedback capacitor, the noise introduced by the stages is substantially reduced. Such switched capacitors can be used in analog to digital converters (ADC).
Abstract translation: 一种开关电容器环境，其中翻转级的反馈电容器以用作下一级的采样电容器。 由于反馈电容器的使用，这些级引入的噪声显着降低。 这种开关电容器可用于模数转换器（ADC）。
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4.发明授权Reducing noise and/or power consumption in a switched capacitor amplifier sampling a reference voltage 有权降低开关电容放大器的噪声和/或功耗，对参考电压进行采样公开(公告)号：US07358801B2
公开(公告)日：2008-04-15
申请号：US11161486
申请日：2005-08-05
Applicant: Sandeep Mallya Perdoor , Visvesvaraya A Pentakota , Ravishankar S Ayyagari
IPC: H03F1/02
CPC classification number: H03F1/26 , H03F1/02 , H03F3/005 , H03F3/45475 , H03F3/45973 , H03F2200/294
Abstract: Equal common mode voltage is present at the input terminals of an operational amplifier with amplifies the residue signal in a stage of an ADC in two phases while reducing the noise introduced into the amplified signal. A reference capacitor is coupled between an input terminal of the operational amplifier and a reference voltage in a first phase, and between the input terminal and a the reference voltage but with opposite polarity in the second phase.
Abstract translation: 在运算放大器的输入端存在相等的共模电压，同时在降低放大信号中引入的噪声的同时放大ADC的一级中的残留信号。 参考电容器耦合在运算放大器的输入端和第一相中的参考电压之间，并且在第二相中在输入端和参考电压之间但极性相反。
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