公开(公告)号：US20050246585A1

公开(公告)日：2005-11-03

申请号：US11085263

申请日：2005-03-22

申请人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Swaine ,  Richard Grisenthwaite

发明人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Swaine ,  Richard Grisenthwaite

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/273

CPC分类号： G06F11/079 ,  G06F11/2733

摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.

摘要翻译： 描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。 当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。

公开(公告)号：US07228457B2

公开(公告)日：2007-06-05

申请号：US10801131

申请日：2004-03-16

申请人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite

发明人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite

IPC分类号： G06F11/00

CPC分类号： G06F11/2236

摘要： A system-on-chip integrated circuit 2 is provided with multiple data processing circuits 4, 6, 8 each with an associated diagnostic interface circuit 16, 18, 20 connected via a diagnostic transaction bus 14 to a diagnostic transaction master circuit 12. The diagnostic master transaction circuit 12 issues diagnostic transaction requests to the diagnostic interface circuits 16, 18, 20. If the associated data processing circuits 4, 6, 8 are powered-down, or otherwise non responsive, then the diagnostic interface circuit 16, 18, 20 returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit 12. A sticky-bit latch 30 within each diagnostic interface circuit 16, 18, 20 serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.

摘要翻译： 系统级芯片集成电路2具有多个数据处理电路4,6,8，每个数据处理电路具有通过诊断事务总线14连接到诊断事务主电路12的相关联的诊断接口电路16,18,20。 诊断主交易电路12向诊断接口电路16,18,20发出诊断事务请求。 如果相关联的数据处理电路4,6,8被断电或以其他方式不响应，则诊断接口电路16,18,20将诊断总线事务错误信号返回给诊断事务主电路12。 每个诊断接口电路16,18,20内的粘滞锁存器30用于记录诊断总线事务错误信号的掉电事件和强制产生，直到诊断机构清除该粘滞位。 这样可以确保诊断机制能够意识到掉电事件，因此可能会由于断电事件而采取任何必要的补救措施。

公开(公告)号：US07251751B2

公开(公告)日：2007-07-31

申请号：US10801132

申请日：2004-03-16

申请人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Brookfield Swaine ,  Michael John Williams

发明人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Brookfield Swaine ,  Michael John Williams

IPC分类号： G06F11/00

CPC分类号： G06F11/366 ,  G06F11/0724 ,  G06F11/079

摘要： Within a system-on-chip device 2 having multiple processing circuits 4, 6, 8, one processing circuit 4 may serve to perform diagnostic operations upon another processing circuit 8 by accessing diagnostic data relating to that other circuit. Thus, one processor may, for example, control and perform halting mode type diagnostic or code profiling upon another.

摘要翻译： 在具有多个处理电路4,6,8的片上系统装置2中，一个处理电路4可用于通过访问与该另一电路有关的诊断数据来对另一处理电路8执行诊断操作。 因此，一个处理器可以例如控制并执行停止模式类型诊断或代码分析。

公开(公告)号：US07426659B2

公开(公告)日：2008-09-16

申请号：US11085263

申请日：2005-03-22

申请人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite

发明人： Conrado Blasco Allue ,  Paul Kimelman ,  Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite

IPC分类号： G06F11/00

CPC分类号： G06F11/079 ,  G06F11/2733

摘要： A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.

摘要翻译： 描述了具有中央处理单元4和诊断机构10的数据处理系统2.中央处理单元4可切换到能够恢复到正常操作模式的掉电模式。 当中央处理单元4恢复到正常操作模式时，诊断机构10禁止程序指令的执行，以允许对诊断机构进行适当的编程，使得立即上电代码和操作能被正确诊断。 通过在断电之前写入诊断机构10内的锁存器16来编程防止上电时程序指令执行的要求。 程序执行的防止可以例如通过产生停止请求或通过在上电之后将中央处理单元4保持在复位的时间段来实现。

公开(公告)号：US07958335B2

公开(公告)日：2011-06-07

申请号：US11197521

申请日：2005-08-05

申请人： Conrado Blasco Allue ,  Glen Andrew Harris ,  Stephen John Hill

发明人： Conrado Blasco Allue ,  Glen Andrew Harris ,  Stephen John Hill

IPC分类号： G06F9/30

CPC分类号： G06F9/3822 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30196

摘要： A method and a data processing apparatus operable to process instructions from a plurality of instruction sets, the plurality of instruction sets each sharing a sub-set of common instructions and each having a remaining set of instructions is disclosed. The data processing apparatus comprises: a plurality of decode units, each decode unit being operable to only decode the remaining set of instructions from a corresponding one of the plurality of instruction sets; and a common decode unit operable to decode a number of the sub-set of common instructions from each of the plurality of instruction sets. This enables the common instructions from each instruction set to be decoded by the common decode unit. Hence, the logic which would otherwise be duplicated in each of the individual decode units for each instruction set can be removed from those decode units and provided just once in the common decode unit. Accordingly, this can significantly reduce the amount of logic duplicated in the decoder units which, in turn, reduces the amount chip area required to support decoding and reduces power consumption. Also, since the decode units are no longer required to support the decoding of such a high number of different instructions, the complexity of each decode unit can be reduced, which can result in increased performance during decode.

摘要翻译： 一种可操作以处理来自多个指令集的指令的方法和数据处理装置，所述多个指令集各自共享公共指令的子集，并且每个具有剩余指令集。 数据处理装置包括：多个解码单元，每个解码单元可操作以仅从所述多个指令集中的相应一个指令集解码所述剩余指令集; 以及公共解码单元，用于从多个指令集中的每一个解码多个公共指令的子集。 这使得来自每个指令集的公共指令由公共解码单元解码。 因此，可以从这些解码单元中删除否则将在每个指令集的各个解码单元中复制的逻辑，并且在公共解码单元中仅提供一次。 因此，这可以显着减少在解码器单元中复制的逻辑量，这反过来减少了支持解码所需的芯片面积的数量并降低功耗。 此外，由于不再需要解码单元来支持这么多数量的不同指令的解码，因此可以减少每个解码单元的复杂度，这可以导致在解码期间增加的性能。

公开(公告)号：US07234043B2

公开(公告)日：2007-06-19

申请号：US11072644

申请日：2005-03-07

申请人： Conrado Blasco Allue ,  Glen Andrew Harris ,  Stephen John Hill

发明人： Conrado Blasco Allue ,  Glen Andrew Harris ,  Stephen John Hill

IPC分类号： G06F9/44

CPC分类号： G06F9/3822 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/382 ,  G06F9/3875

摘要： Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.

摘要翻译： 在支持预测指令的多指令流水线数据处理系统中，在假定它们被预测的情况下，程序指令最初被解码。 当检测到预测指令时，在指令解码器级内产生预测信号。 然后可以使用该预测信号的存在或不存在来校正已经基于假定程序指令被预测的方式执行的任何解码。 预测指令可以说明可变数量的以下指令。 预测指令可以与其所预测的指令并行地发出，然而在至少对其他程序指令进行了一些解码之前，不需要确认预测指令的正确识别。

公开(公告)号：US20060200653A1

公开(公告)日：2006-09-07

申请号：US11072644

申请日：2005-03-07

申请人： Conrado Blasco Allue ,  Glen Harris ,  Stephen Hill

发明人： Conrado Blasco Allue ,  Glen Harris ,  Stephen Hill

IPC分类号： G06F9/44

CPC分类号： G06F9/3822 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/382 ,  G06F9/3875

摘要： Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages when a predication instruction is detected. The presence or absence of this predication signal can then be used to correct any decoding which has been performed upon the basis of an assumption that the program instructions are predicated. The predication instruction can predicate a variable number of following instructions. The predication instruction can issue in parallel with an instruction which it predicates and yet the proper identification of the predication instruction need not be confirmed until at least some decoding has been performed upon the other program instruction.

摘要翻译： 在支持预测指令的多指令流水线数据处理系统中，在假定它们被预测的情况下，程序指令最初被解码。 当检测到预测指令时，在指令解码器级内产生预测信号。 然后可以使用该预测信号的存在或不存在来校正已经基于假定程序指令被预测的方式执行的任何解码。 预测指令可以说明可变数量的以下指令。 预测指令可以与其所预测的指令并行地发出，然而在至少对其他程序指令进行了一些解码之前，不需要确认预测指令的正确识别。

公开(公告)号：US09081581B2

公开(公告)日：2015-07-14

申请号：US12926414

申请日：2010-11-16

申请人： James Nolan Hardage ,  Conrado Blasco Allue ,  Glen Andrew Harris

发明人： James Nolan Hardage ,  Conrado Blasco Allue ,  Glen Andrew Harris

IPC分类号： G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3842

摘要： An out-of-order processor 4 groups program instructions together to control their commitment to complete processing. If an instruction within a group has a source operand dependent upon a plurality of destination operands of other instructions then this is identified as a size mismatch hazard. When the program instruction having the size mismatch hazard reaches a commit point within the processor, then it is flushed together with any speculatively executed succeeding program instructions. Furthermore, the group of program instructions containing the program instruction containing the program instruction having the size mismatch is divided into a plurality of groups of program instructions each containing a single program instruction which are then replayed through the processing mechanisms.

摘要翻译： 无序处理器将程序指令组合在一起，以控​​制其完成处理的承诺。 如果组内的指令具有取决于其他指令的多个目的地操作数的源操作数，则将其识别为大小不匹配危险。 当具有大小不匹配危险的程序指令到达处理器内的提交点时，它与任何推测性执行的后续程序指令一起被刷新。 此外，包含包含具有尺寸不匹配的程序指令的程序指令的程序指令组被划分为多个程序指令组，每组程序指令都包含单个程序指令，然后通过处理机制重播程序指令。

公开(公告)号：US20100306505A1

公开(公告)日：2010-12-02

申请号：US12457124

申请日：2009-06-01

申请人： David James Williamson ,  Conrado Blasco Allue

发明人： David James Williamson ,  Conrado Blasco Allue

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3828

摘要： A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register 32 storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.

摘要翻译： 处理器2包括具有多个执行单元14,16,18,20的执行群集10.执行单元14,16,18,20共享结果总线22,24。执行群集10内的发行电路12确定未来的可用性 结果总线22,24用于使用该指令的已知周期计数来发出（或最近发布）的指令。 使用存储掩码值的掩码寄存器32跟踪每个结果总线的可用性，其中每个位位置指示将来在特定处理周期的该结果总线的可用性或不可用性。 掩码值在每个处理周期左移。

公开(公告)号：US20100332805A1

公开(公告)日：2010-12-30

申请号：US12457905

申请日：2009-06-24

申请人： Conrado Blasco Allue ,  David James Williamson ,  James Nolan Hardage ,  Glen Andrew Harris ,  Robert Gregory McDonald

发明人： Conrado Blasco Allue ,  David James Williamson ,  James Nolan Hardage ,  Glen Andrew Harris ,  Robert Gregory McDonald

IPC分类号： G06F9/30

CPC分类号： G06F9/30112 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384

摘要： An out-of-order renaming processor is provided with a register file within which aliasing between registers of different sizes may occur. In this way a program instruction having a source register of a double precision size may alias with two single precision registers being used as destinations of one or more preceding program instructions. In order to track this data dependency the double precision register may be remapped into a micro-operation specifying two single precision registers as its source register. In this way, scheduling circuitry may use its existing hazard detection and management mechanisms to handle potential data hazards and dependencies. Not all program instructions having such data hazards between registers of different sizes are handled by this source register remapping. For these other program instructions a slower mechanism for dealing with the data dependency hazard is provided. This slower mechanism may, for example, be to drain all the preceding micro-operations from the execution pipelines before issuing the micro-operation having the data hazard.

摘要翻译： 无序重命名处理器具有寄存器文件，在该寄存器文件中可能发生不同大小的寄存器之间的混叠。 以这种方式，具有双精度尺寸的源寄存器的程序指令可以使用两个单精度寄存器作为一个或多个先前程序指令的目的地。 为了跟踪这种数据依赖关系，双精度寄存器可以重新映射成指定两个单精度寄存器作为其源寄存器的微操作。 以这种方式，调度电路可以使用其现有的危险检测和管理机制来处理潜在的数据危害和依赖性。 并不是所有具有不同大小的寄存器之间的数据危害的程序指令都由该源寄存器重新映射来处理。 对于这些其他程序指令，提供了一种用于处理数据依赖性危害的较慢机制。 例如，这种较慢的机制可能在发出具有数据危险的微操作之前从执行管线中排出所有先前的微操作。