Low-noise amplifier
    1.
    发明授权
    Low-noise amplifier 有权
    低噪声放大器

    公开(公告)号:US08264276B2

    公开(公告)日:2012-09-11

    申请号:US12966761

    申请日:2010-12-13

    IPC分类号: H03F3/45

    摘要: Traditionally, low-noise amplifiers or LNAs have been used in high frequency applications, but for very high frequency ranges (i.e., 60 GHz), building an LNA to meet performance needs has been difficult. Here, however, an LNA has been provided that operates well around 60 GHz. In particularly, this LNA is generally unconditionally stable, has a generally low noise factor or NF, and has a generally high gain around 60 GHz.

    摘要翻译: 传统上,在高频应用中已经使用低噪声放大器或LNA,但是对于非常高的频率范围(即60GHz),建立LNA以满足性能需求是困难的。 然而,在这里,已经提供了在60GHz左右运行的LNA。 特别地,该LNA通常是无条件稳定的,具有通常低的噪声因子或NF,并且在60GHz附近具有通常较高的增益。

    Vector reads for array updates
    2.
    发明申请
    Vector reads for array updates 有权
    向量读取数组更新

    公开(公告)号:US20050262110A1

    公开(公告)日:2005-11-24

    申请号:US10848869

    申请日:2004-05-18

    IPC分类号: G06F7/00 G06F17/30

    CPC分类号: G06F17/30315

    摘要: An array update operation which specifies number of (row-identifier, value) pairs for updating rows in a table of a database is implemented as follows. A block-identifier of a block (on disk) that holds a row identified by a row-identifier in a specified pair is looked up using a database index, and the block-identifier thus found is stored in a structure. Use of a row-identifier to look up the corresponding block-identifier, and the storage of the block-identifier in the structure are repeatedly performed, for each of several specified pairs. Next, a vector read is performed, to read and store in a cache, each block identified by a block-identifier in the structure, and all the blocks that have been read are stored in the cache during a single function call. Thereafter, rows identified in specified pairs are modified, in blocks currently in the cache, using the values in the specified pairs.

    摘要翻译: 指定数据库表中更新行的(行标识符,值)对数的数组更新操作如下。 使用数据库索引来查找保存由指定对中的行标识符标识的行的块(在磁盘上)的块标识符,并且由此找到的块标识符被存储在结构中。 对于几个指定的对中的每一个,重复执行使用行标识符来查找对应的块标识符,并且对结构中的块标识符的存储被重复执行。 接下来,执行向量读取,以读取和存储在高速缓存中,由结构中的块标识符标识的每个块以及所读取的所有块在单个功能调用期间被存储在高速缓存中。 此后,使用指定对中的值,以当前在高速缓存中的块中修改以指定对标识的行。

    Systems and Methods for Cancelling Phase-Locked Loop Supply Noise
    3.
    发明申请
    Systems and Methods for Cancelling Phase-Locked Loop Supply Noise 有权
    取消锁相环路供电噪声的系统和方法

    公开(公告)号:US20090295440A1

    公开(公告)日:2009-12-03

    申请号:US12131982

    申请日:2008-06-03

    申请人: Richard Gu

    发明人: Richard Gu

    IPC分类号: H03L7/06 H03K5/00

    CPC分类号: H03L7/093 H03L7/0895

    摘要: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

    摘要翻译: 用于消除电源噪声的装置的一个实施例包括可操作以从电荷泵接收输入的输入电路和连接到输入电路的输出的驱动电路。 驱动电路可操作以在输入电路和驱动电路供电的电压源稳定时向输入电路提供匹配输入的输出,并且当电压源噪声时对缓冲输出引入相反的电压变化, 相反的电压变化与由于噪声导致的电压源上的电压变化相反。

    Charge pump output device with leakage cancellation
    4.
    发明授权
    Charge pump output device with leakage cancellation 有权
    带有泄漏消除的电荷泵输出装置

    公开(公告)号:US07157962B2

    公开(公告)日:2007-01-02

    申请号:US10940197

    申请日:2004-09-13

    申请人: Richard Gu

    发明人: Richard Gu

    IPC分类号: H03K17/16 H03K19/003

    CPC分类号: H02M3/07

    摘要: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

    摘要翻译: 电荷泵电路包括:电荷泵输出分支; 耦合到所述输出分支的电流泄漏装置; 以及耦合在所述电流泄漏装置的输出支路和控制节点之间的反馈装置,使得所述泄漏装置抵消来自所述输出支路的泄漏电流。

    Rail-to-rail charge pump with replica circuitry
    5.
    发明授权
    Rail-to-rail charge pump with replica circuitry 有权
    轨至轨电荷泵,带复制电路

    公开(公告)号:US07123085B2

    公开(公告)日:2006-10-17

    申请号:US10940375

    申请日:2004-09-14

    申请人: Richard Gu

    发明人: Richard Gu

    IPC分类号: G05F1/02 H03L7/093

    CPC分类号: H02M3/07

    摘要: The charge pump circuit includes: a charge pump output branch having a first transistor and a second transistor coupled in series; an output branch replica having a third transistor and a fourth transistor coupled in series; a feedback circuit coupled between the output branch and the output branch replica; a charge pump input circuit coupled to the charge pump output branch, and having first and second input branches; and an input circuit branch replica controlled by the feedback circuit and coupled to the charge pump input circuit.

    摘要翻译: 电荷泵电路包括:电荷泵输出支路,具有串联耦合的第一晶体管和第二晶体管; 输出分支副本,具有串联耦合的第三晶体管和第四晶体管; 耦合在输出分支和输出分支副本之间的反馈电路; 电荷泵输入电路,耦合到电荷泵输出分支,并具有第一和第二输入分支; 以及由反馈电路控制并耦合到电荷泵输入电路的输入电路分支复制品。

    Time division multiplex data recovery system using close loop phase and delay locked loop
    6.
    发明授权
    Time division multiplex data recovery system using close loop phase and delay locked loop 有权
    时分复用数据恢复系统采用闭环相位和延迟锁相环

    公开(公告)号:US06901126B1

    公开(公告)日:2005-05-31

    申请号:US09607772

    申请日:2000-06-30

    申请人: Richard Gu

    发明人: Richard Gu

    摘要: A time division multiplex data recovery system using a closed-loop phase lock loop (PLL) and delay locked loop (DLL) is disclosed. In other words, one closed loop comprises both a phase locked loop (PLL) and a delay locked loop (DLL) in a novel time division multiplex data recovery system. This new architecture comprises a 4 stage Voltage Controlled Oscillator (VCO) used to generate 8 clock signals, 45 degrees phase shifted from one another, for 8 receivers to do the oversampling. An interpolator tracks the received data signal and feeds it back to the Phase/Frequency Detector (PFD). The PFD has a second input of the reference clock which the PFD uses along with the interpolator input to correct the frequency of the PLL. The PLL operates at a high bandwidth. The DLL's bandwidth is several orders lower than the PLL. The DLL activates only a multiplexer and an interpolator continuously, thereby drawing a minimum amount of power.

    摘要翻译: 公开了一种使用闭环锁相环(PLL)和延迟锁定环(DLL)的时分复用数据恢复系统。 换句话说,一个闭环包括新颖的时分复用数据恢复系统中的锁相环(PLL)和延迟锁定环(DLL)。 这种新架构包括4级压控振荡器(VCO),用于生成8个时钟信号,相互相移45度,8个接收器进行过采样。 内插器跟踪接收的数据信号并将其反馈到相位/频率检测器(PFD)。 PFD具有参考时钟的第二个输入,PFD与内插器输入一起使用,以校正PLL的频率。 PLL在高带宽下工作。 DLL的带宽比PLL低几个数量级。 DLL仅连续激活多路复用器和内插器,从而绘制最小的功率。

    IN-MEMORY-DATABASE-DRIVEN BUSINESS CONSOLIDATION SYSTEM REPORTING
    8.
    发明申请
    IN-MEMORY-DATABASE-DRIVEN BUSINESS CONSOLIDATION SYSTEM REPORTING 审中-公开
    内存数据库驱动业务合并系统报告

    公开(公告)号:US20150039478A1

    公开(公告)日:2015-02-05

    申请号:US13960457

    申请日:2013-08-06

    IPC分类号: G06Q40/00

    CPC分类号: G06Q40/12

    摘要: The present disclosure describes methods, systems, and computer program products for providing enhanced business consolidation system reporting functionality according to an implementation. One computer-implemented method includes retrieving financial journal entry data from a total record for consolidation into a consolidated financial report, the financial journal entry data classified as single company closing records, inter-company elimination records, and group-dependent elimination records, processing the single company closing records resulting in single company closing records result data, processing the inter-company elimination records resulting in inter-company elimination records result data, processing the group-dependent elimination records resulting in group-dependent elimination records result data, performing, by operation of a computer, a union of the single company closing records result data, the inter-company elimination records result data, and the group-dependent elimination records result data to generate consolidated financial report data, and generating a consolidated financial report based, at least in part, on the consolidated financial report data.

    摘要翻译: 本公开描述了根据实现提供增强的业务合并系统报告功能的方法,系统和计算机程序产品。 一种计算机实现的方法包括从总记录中将财务日记帐分录数据从合并到合并财务报告中,将金融日记账分录数据分类为单个公司关闭记录,公司间消除记录和组依赖消除记录,处理 单个公司关闭记录导致单个公司关闭记录结果数据,处理公司间消除记录,导致公司间消除记录结果数据,处理依赖于组的消除记录,导致依赖于组的消除记录结果数据,执行,由 计算机的运作,单一公司的联合关闭记录结果数据,公司间消除记录结果数据,以及组依赖的淘汰记录结果数据,以生成合并财务报表数据,并根据 至少部分归功于综合财务报告 数据。

    Systems and methods for cancelling phase-locked loop supply noise
    9.
    发明授权
    Systems and methods for cancelling phase-locked loop supply noise 有权
    消除锁相环电源噪声的系统和方法

    公开(公告)号:US08674753B2

    公开(公告)日:2014-03-18

    申请号:US12131982

    申请日:2008-06-03

    申请人: Richard Gu

    发明人: Richard Gu

    IPC分类号: H03B1/00 H03K5/00 H04B1/10

    CPC分类号: H03L7/093 H03L7/0895

    摘要: One embodiment of an apparatus for cancelling supply noise includes an input circuit operable to receive an input from a charge pump and a drive circuit connected to an output of the input circuit. The drive circuit is operable to provide an output matching the input to the input circuit when a voltage source powering the input circuit and the drive circuit is stable, and to introduce a contrary voltage change on the buffered output when the voltage source is noisy, with the contrary voltage change being contrary to a voltage change on the voltage source due to noise.

    摘要翻译: 用于消除电源噪声的装置的一个实施例包括可操作以从电荷泵接收输入的输入电路和连接到输入电路的输出的驱动电路。 驱动电路可操作以在输入电路和驱动电路供电的电压源稳定时向输入电路提供匹配输入的输出,并且当电压源噪声时对缓冲输出引入相反的电压变化, 相反的电压变化与由于噪声导致的电压源上的电压变化相反。

    Latch divider
    10.
    发明授权
    Latch divider 有权
    锁扣分配器

    公开(公告)号:US08456202B2

    公开(公告)日:2013-06-04

    申请号:US13028003

    申请日:2011-02-15

    IPC分类号: H03K21/00 H03K23/00

    CPC分类号: H03B19/14

    摘要: There are numerous types of dividers that have been employed at various frequency ranges. For many very high frequency ranges (i.e., above 30 GHz), dividers in CMOS have been developed. However, many of these designs use multiple stages. Here, however, a single stage divider has been provided that is adapted to operate at very high frequencies (i.e., 120 GHz). To accomplish this, it uses parasitic capacitances in conjunction with inductor(s) to form an LC tanks so as to take advantages of parasitics that normal degrade performance.

    摘要翻译: 在各种频率范围内使用了多种类型的分频器。 对于许多非常高的频率范围(即,高于30GHz),已经开发了CMOS中的分频器。 然而,许多这些设计使用多个阶段。 然而,这里提供了适用于在非常高的频率(即120GHz)下工作的单级分频器。 为了实现这一点,它使用寄生电容与电感器一起形成LC箱,以便利用正常退化性能的寄生效应。