公开(公告)号：US20210320875A1

公开(公告)日：2021-10-14

申请号：US17357358

申请日：2021-06-24

申请人： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas E. Willis ,  Timothy Verrall ,  Robert G. Southworth

发明人： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas E. Willis ,  Timothy Verrall ,  Robert G. Southworth

IPC分类号： H04L12/851

摘要： A network switch includes a memory device to store a stream information of a plurality of data streams being handled by the network switch, the stream information including a stream identifier, a stream service level agreement (SLA), and a stream traffic type; accelerator circuitry to apply stream transformation functions to data streams; telemetry circuitry to monitor egress ports of the network switch; and scheduler circuitry to: receive telemetry data from the telemetry circuitry to determine that a utilization of egress ports of the network switch is over a threshold utilization; determine a selected data stream of the plurality of data streams to transform; use the accelerator circuitry to transform the selected data stream to produce a transformed data stream, wherein the transformed data stream complies with a corresponding stream SLA; and transmit the transformed data stream on an egress port.

公开(公告)号：US20170093709A1

公开(公告)日：2017-03-30

申请号：US14866180

申请日：2015-09-25

申请人： Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

发明人： Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

IPC分类号： H04L12/741 ,  H04L29/06

摘要： A cyclic redundancy code (CRC) update device includes an input coupled to obtain an old CRC that corresponds to an old header of a communication packet, a CRC storage device to store CRC coefficients, a CRC calculator coupled to receive a modified old header of the communication packet and calculate a new CRC on the modified old header, and a polynomial multiplier coupled to the CRC storage device to receive the new CRC, obtain a corresponding coefficient from the CRC storage device, and generate an update for the CRC of the frame.

公开(公告)号：US20150341277A1

公开(公告)日：2015-11-26

申请号：US14284034

申请日：2014-05-21

申请人： Alain Gravel ,  Robert G. Southworth ,  Jonathan A. Dama ,  Ilango S. Ganga ,  Matthew J. Webb

发明人： Alain Gravel ,  Robert G. Southworth ,  Jonathan A. Dama ,  Ilango S. Ganga ,  Matthew J. Webb

IPC分类号： H04L12/825 ,  H04L1/00 ,  H04L7/033 ,  H04L12/931

CPC分类号： H04L47/25 ,  H04J3/0697 ,  H04L1/00 ,  H04L1/0002 ,  H04L1/0041 ,  H04L1/0045 ,  H04L7/033 ,  H04L7/0331 ,  H04L12/413 ,  H04L25/14 ,  H04L25/49 ,  H04L49/352

摘要： Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

摘要翻译： 用于高速数据传输的技术，包括具有耦合到物理介质依赖/物理介质连接（PMD / PMA）子层的通信通道的网络端口逻辑，物理编码子层（PCS）和媒体访问控制（MAC）子层 。 通信通道以25吉比特每秒的线速度接收串行二进制数据。 PMD / PMA将串行二进制数据转换成并行数据，并且PCS使用也用于较慢线速度（例如10吉比特每秒）的线路码解码该并行数据。 网络端口逻辑可以包括四个独立的通信通道，每个通信通道耦合到专用PMD / PMA，PCS和MAC。 网络端口逻辑还可以包括多通道PCS和多通道MAC，用于接收和发送在四个通信通道上划分的数据。 描述和要求保护其他实施例。

公开(公告)号：US20170286006A1

公开(公告)日：2017-10-05

申请号：US15088726

申请日：2016-04-01

申请人： Sanjeev Jain ,  Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

发明人： Sanjeev Jain ,  Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

IPC分类号： G06F3/06 ,  H04L29/08

CPC分类号： G06F12/023 ,  G06F9/54 ,  G06F12/0292 ,  G06F2212/1024 ,  G06F2212/1044 ,  Y02D10/13

摘要： Apparatuses and methods for pipelined hashing are described herein. An example apparatus to perform a pipelined hash function may include a first memory to store a first plurality of bucket records, a second memory to store a second plurality of bucket records, and a hash circuit to receive a key and to perform a pipelined hash function using the key to provide a hash value. The hash circuit further to select a first bucket record of the first plurality of bucket records from the first memory based on a first subset of bits of the hash value. The hash circuit further to provide a location of a particular entry of an entry record of the plurality of entry records based on contents of the first bucket record and a second subset of bits of the hash value.

公开(公告)号：US20170093708A1

公开(公告)日：2017-03-30

申请号：US14865868

申请日：2015-09-25

申请人： Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

发明人： Karl S. Papadantonakis ,  Robert G. Southworth ,  Alain Gravel ,  Jonathan A. Dama

IPC分类号： H04L12/741 ,  H04L29/06

CPC分类号： H04L45/74 ,  H04L49/3009 ,  H04L69/22

摘要： A communication packet processing device may include a control stage coupled to receive multiple headers of a packet comprised of multiple words, and to determine a destination lane for each word of the multiple headers by counting previous words of the headers. The device may also include a level 1 permutation circuit coupled to the control stage to place each word into a correct lane responsive to the determined destination lane, and a level 2 permutation circuit coupled to the level 1 permutation t circuit o place each word into a correct designation lane responsive to the determined destination lane. Additional embodiments are also described.