Method and apparatus for leveling a semiconductor wafer, and semiconductor wafer with improved flatness
    1.
    发明授权
    Method and apparatus for leveling a semiconductor wafer, and semiconductor wafer with improved flatness 失效
    用于使半导体晶片调平的方法和装置以及具有改善的平坦度的半导体晶片

    公开(公告)号:US07407891B2

    公开(公告)日:2008-08-05

    申请号:US11268356

    申请日:2005-11-07

    IPC分类号: H01L21/302

    摘要: Semiconductor wafers are leveled by position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate. Semiconductor wafers with improved flatness and nanotopography, and SOI wafers with improved layer thickness homogeneity are produced by this process.

    摘要翻译: 通过晶片表征参数的位置相关测量对半导体晶片进行调平,以在半导体晶片的整个表面上确定该参数的位置相关值,同时在蚀刻介质的作用下蚀刻半导体晶片的整个表面 随着整个表面的同时照明,材料去除蚀刻速率取决于半导体晶片表面处的光强度,光强度以位置相关的方式被建立,使得位置相关值的差异 在步骤a)中测量的参数被依赖于位置的材料去除率降低。 通过该方法产生具有改善的平坦度和纳米形貌的半导体晶片和具有改善的层厚均匀性的SOI晶片。

    Layered Semiconductor Wafer With Low Warp And Bow, And Process For Producing It
    2.
    发明申请
    Layered Semiconductor Wafer With Low Warp And Bow, And Process For Producing It 有权
    具有低翘曲和弓形的分层半导体晶圆及其生产工艺

    公开(公告)号:US20080122043A1

    公开(公告)日:2008-05-29

    申请号:US12023102

    申请日:2008-01-31

    IPC分类号: H01L23/58 H01L21/02

    CPC分类号: H01L21/2007

    摘要: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

    摘要翻译: 直径为至少200mm的半导体晶片包括硅载体晶片,电绝缘层和位于其上的半导体层,半导体晶片已经通过包括至少一个RTA步骤的层转移工艺生产,其中半导体 晶片具有小于30μm的翘曲,小于30μm的DeltaWarp,小于10μm的弓和小于10um的DeltaBow。 用于生产这种类型的半导体晶片的方法需要特定的热处理方案。

    Method and apparatus for leveling a semiconductor wafer, and semiconductor wafer with improved flatness
    3.
    发明申请
    Method and apparatus for leveling a semiconductor wafer, and semiconductor wafer with improved flatness 失效
    用于使半导体晶片调平的方法和装置以及具有改善的平坦度的半导体晶片

    公开(公告)号:US20060097355A1

    公开(公告)日:2006-05-11

    申请号:US11268356

    申请日:2005-11-07

    IPC分类号: H01L29/06 H01L21/461 C23F1/00

    摘要: Semiconductor wafers are leveled by a) position-dependent measurement of a wafer-characterizing parameter to determine the position-dependent value of this parameter over an entire surface of the semiconductor wafer, b) etching the entire surface of the semiconductor wafer simultaneously under the action of an etching medium with simultaneous illumination of the entire surface, the material-removal etching rate dependent on the light intensity at the surface of the semiconductor wafer, the light intensity being established in a position-dependent manner such that the differences in the position-dependent values of the parameter measured in step a) are reduced by the position-dependent material-removal rate, semiconductor wafers with improved flatness and nanotopography and SOI wafer with improved layer thickness homogeneity are achieved. An apparatus for carrying out the method is also disclosed.

    摘要翻译: 半导体晶片通过a)晶圆表征参数的位置相关测量来平坦化,以确定该参数在半导体晶片的整个表面上的位置相关值,b)在动作下同时蚀刻半导体晶片的整个表面 具有同时照射整个表面的蚀刻介质,所述材料去除蚀刻速率取决于半导体晶片的表面处的光强度,所述光强度以位置相关的方式建立,使得位置依赖性的差异, 在步骤a)中测量的参数的相关值通过位置相关的材料去除率降低,具有改善的平坦度的半导体晶片和纳米形貌以及具有改善的层厚度均匀性的SOI晶片被实现。 还公开了一种用于执行该方法的装置。

    Layered semiconductor wafer with low warp and bow, and process for producing it
    5.
    发明授权
    Layered semiconductor wafer with low warp and bow, and process for producing it 有权
    具有低经纱和弓形的分层半导体晶片及其生产工艺

    公开(公告)号:US07820549B2

    公开(公告)日:2010-10-26

    申请号:US12023102

    申请日:2008-01-31

    IPC分类号: H01L21/20

    CPC分类号: H01L21/2007

    摘要: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

    摘要翻译: 直径为至少200mm的半导体晶片包括硅载体晶片,电绝缘层和位于其上的半导体层,半导体晶片已经通过包括至少一个RTA步骤的层转移工艺生产,其中半导体 晶片的翘曲小于30μm,DeltaWarp小于30μm,弓形小于10μm,DeltaBow小于10μm。 用于生产这种类型的半导体晶片的方法需要特定的热处理方案。

    Layered semiconductor wafer with low warp and bow, and process for producing it
    7.
    发明申请
    Layered semiconductor wafer with low warp and bow, and process for producing it 审中-公开
    具有低经纱和弓形的分层半导体晶片及其生产工艺

    公开(公告)号:US20060046431A1

    公开(公告)日:2006-03-02

    申请号:US11206599

    申请日:2005-08-18

    IPC分类号: H01L21/30

    CPC分类号: H01L21/2007

    摘要: Semiconductor wafers with a diameter of at least 200 mm comprise a silicon carrier wafer, an electrically insulating layer and a semiconductor layer located thereon, the semiconductor wafer having been produced by means of a layer transfer process comprising at least one RTA step, wherein the semiconductor wafer has a warp of less than 30 μm, a DeltaWarp of less than 30 μm, a bow of less than 10 μm and a DeltaBow of less than 10 μm. Processes for the production of a semiconductor wafer of this type require specific heat treatment regimens.

    摘要翻译: 直径为至少200mm的半导体晶片包括硅载体晶片,电绝缘层和位于其上的半导体层,半导体晶片已经通过包括至少一个RTA步骤的层转移工艺生产,其中半导体 晶片具有小于30μm的翘曲,小于30μm的DeltaWarp,小于10μm的弓和小于10um的DeltaBow。 用于生产这种类型的半导体晶片的方法需要特定的热处理方案。