公开(公告)号：US07974997B2

公开(公告)日：2011-07-05

申请号：US11731174

申请日：2007-03-30

申请人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

发明人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

IPC分类号： G06F17/16

CPC分类号： G06F17/16 ,  H04B1/707 ,  H04B2201/70707 ,  H04B2201/709727

摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

摘要翻译： 在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。 所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。 基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。 至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。 两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

公开(公告)号：US20080243982A1

公开(公告)日：2008-10-02

申请号：US11731174

申请日：2007-03-30

申请人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

发明人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

IPC分类号： G06F17/10 ,  G06F7/32

CPC分类号： G06F17/16 ,  H04B1/707 ,  H04B2201/70707 ,  H04B2201/709727

摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

摘要翻译： 在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。 所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。 基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。 至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。 两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

公开(公告)号：US4517231A

公开(公告)日：1985-05-14

申请号：US416797

申请日：1982-09-13

申请人： Joseph R. May ,  Frank Petruccelli ,  Robert L. Lang ,  Herman P. de Haan

发明人： Joseph R. May ,  Frank Petruccelli ,  Robert L. Lang ,  Herman P. de Haan

IPC分类号： B29C41/06 ,  B29C41/20 ,  B65D90/52 ,  B32B1/02 ,  B32B27/00

CPC分类号： B65D90/52 ,  B29C41/06 ,  B29C41/20 ,  B60K15/077 ,  B60K15/03177 ,  B60K2015/03453 ,  B60K2015/03467 ,  B60K2015/0775 ,  B60K2015/0777 ,  Y10T428/1397

摘要： A hollow, enclosed, seamless polymeric article. The article has an outer wall having an outside surface and an inside surface. There is at least one baffle within the article. There is a means to sealingly connect the baffle to the outer wall inside the article. The means to sealingly connect the baffle can sealingly connect the baffle to the inside surface of the outer wall or through the inner surface into the outer wall.

摘要翻译： 中空封闭的无缝聚合物品。 该制品具有外壁和内表面的外壁。 文章中至少有一个挡板。 有一种将挡板密封连接到制品内的外壁的方法。 密封连接挡板的方法可以将挡板密封地连接到外壁的内表面或通过内表面连接到外壁。