公开(公告)号：US07974997B2

公开(公告)日：2011-07-05

申请号：US11731174

申请日：2007-03-30

申请人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

发明人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

IPC分类号： G06F17/16

CPC分类号： G06F17/16 ,  H04B1/707 ,  H04B2201/70707 ,  H04B2201/709727

摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

摘要翻译： 在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。 所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。 基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。 至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。 两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

公开(公告)号：US20080243982A1

公开(公告)日：2008-10-02

申请号：US11731174

申请日：2007-03-30

申请人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

发明人： Eliahou Arviv ,  Robert L. Lang ,  Yi-Chen Li ,  Oliver Ridler ,  Xiao-an Wang

IPC分类号： G06F17/10 ,  G06F7/32

CPC分类号： G06F17/16 ,  H04B1/707 ,  H04B2201/70707 ,  H04B2201/709727

摘要： In one embodiment, a receiver including one or more signal-processing blocks and a hardware-based matrix co-processor. The one or more signal-processing blocks are adapted to generate a processed signal from a received signal. The hardware-based matrix co-processor includes two or more different matrix-computation engines, each adapted to perform a different matrix computation, and one or more shared hardware-computation units, each adapted to perform a mathematical operation. At least one signal-processing block is adapted to offload matrix-based signal processing to the hardware-based matrix co-processor. Each of the two or more different matrix-computation engines is adapted to offload the same type of mathematical processing to at least one of the one or more shared hardware-computation units.

摘要翻译： 在一个实施例中，接收机包括一个或多个信号处理块和基于硬件的矩阵协处理器。 所述一个或多个信号处理块适于从接收到的信号产生经处理的信号。 基于硬件的矩阵协处理器包括两个或更多个不同的矩阵计算引擎，每个矩阵计算引擎适于执行不同的矩阵计算，以及一个或多个共享硬件计算单元，每个共享硬件计算单元适于执行数学运算。 至少一个信号处理块适于将基于矩阵的信号处理卸载到基于硬件的矩阵协处理器。 两个或更多个不同的矩阵计算引擎中的每一个适于将相同类型的数学处理卸载到一个或多个共享硬件计算单元中的至少一个。

公开(公告)号：US20130077464A1

公开(公告)日：2013-03-28

申请号：US13245098

申请日：2011-09-26

申请人： Leonid Dubrovin ,  Alexander Rabinovitch ,  Eliahou Arviv

发明人： Leonid Dubrovin ,  Alexander Rabinovitch ,  Eliahou Arviv

IPC分类号： H04J11/00 ,  H04W92/00

CPC分类号： H04J13/12 ,  H04J13/0044

摘要： An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of first code bits in response to an index value and (ii) a plurality of first intermediate bits in response to the index value. The first code bits may be generated in parallel with the first intermediate bits. The second circuit may be configured to generate a plurality of second code bits in response to all of (i) the index value, (ii) the first code bits and (iii) the first intermediate bits. A combination of the first code bits and the second code bits generally forms one of a plurality of orthogonal codes.

摘要翻译： 公开了一种通常具有第一电路和第二电路的装置。 第一电路可以被配置为响应于索引值产生（i）多个第一码位，并且响应于索引值，产生多个第一中间位。 可以与第一中间位并行地生成第一码位。 第二电路可以被配置为响应于（i）索引值，（ii）第一码位和（iii）第一中间位的全部产生多个第二码位。 第一码位和第二码位的组合通常形成多个正交码中的一个。

公开(公告)号：US20120155579A1

公开(公告)日：2012-06-21

申请号：US12974039

申请日：2010-12-21

申请人： Gennady Zilberman ,  Eliahou Arviv ,  Daniel Briker ,  Gil Naveh ,  Moshe Bukris

发明人： Gennady Zilberman ,  Eliahou Arviv ,  Daniel Briker ,  Gil Naveh ,  Moshe Bukris

IPC分类号： H04L27/06

CPC分类号： H04L25/03891 ,  H04L25/0246 ,  H04L25/03216

摘要： A method of detecting received data in a communication system includes the steps of: performing a QR decomposition on a received input vector as a function of one or more characteristics of a communication channel over which the input vector was transmitted; generating a subset of best symbol candidates from a symbol constellation by comparing an input sample (corresponding to an element of the input vector) with one or more prescribed thresholds; identifying at least one symbol satisfying prescribed minimum Euclidian distance criteria among multiple ambiguity symbols in the subset of best symbol candidates; and generating a subset of best symbols including a prescribed number of symbols from the symbol constellation determined to be closest to the input sample. The subset of best symbols is used in a subsequent iteration of the steps of generating the subset of best symbol candidates and identifying at least one symbol satisfying the prescribed minimum Euclidian distance criteria.

摘要翻译： 一种在通信系统中检测接收到的数据的方法包括以下步骤：根据所传送的输入向量的通信信道的一个或多个特征，对所接收的输入向量执行QR分解; 通过将输入样本（对应于输入向量的元素）与一个或多个规定阈值进行比较，从符号星座生成最佳符号候选的子集; 识别在最佳符号候选的子集中的多个模糊符号中满足规定的最小欧几里德距离标准的至少一个符号; 以及从确定为最接近所述输入样本的所述符号星座生成包括规定数量的符号的最佳符号的子集。 最佳符号的子集用于生成最佳符号候选的子集的步骤的后续迭代，并且识别满足规定的最小欧几里德距离标准的至少一个符号。

公开(公告)号：US20100027592A1

公开(公告)日：2010-02-04

申请号：US12181624

申请日：2008-07-29

申请人： Eliahou Arviv ,  Daniel Briker ,  Gennady Zilberman

发明人： Eliahou Arviv ,  Daniel Briker ,  Gennady Zilberman

IPC分类号： H04B1/707

CPC分类号： H04B1/7075 ,  H04B2001/70935

摘要： In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.

摘要翻译： 在一个实施例中，公开了一种用于解调和搜索包含复相量信号的前同步信号的方法。 使用相量旋转的快速变压器对复相量进行解调。 接收到的信号与扩展码相关以产生相关信号。 相关信号被相干累积以产生相干累积信号。 对相干累加信号的实分量执行第一相量旋转信号变换，并对相干累加信号的虚分量执行第二相量旋转信号变换。 最后，确定相干累加信号的变换的实分量和虚分量的信号功率。

公开(公告)号：US08891351B2

公开(公告)日：2014-11-18

申请号：US13245098

申请日：2011-09-26

申请人： Leonid Dubrovin ,  Alexander Rabinovitch ,  Eliahou Arviv

发明人： Leonid Dubrovin ,  Alexander Rabinovitch ,  Eliahou Arviv

IPC分类号： H04J11/00 ,  H04J13/00 ,  H04J13/12

CPC分类号： H04J13/12 ,  H04J13/0044

摘要： An apparatus generally having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate (i) a plurality of first code bits in response to an index value and (ii) a plurality of first intermediate bits in response to the index value. The first code bits may be generated in parallel with the first intermediate bits. The second circuit may be configured to generate a plurality of second code bits in response to all of (i) the index value, (ii) the first code bits and (iii) the first intermediate bits. A combination of the first code bits and the second code bits generally forms one of a plurality of orthogonal codes.

摘要翻译： 公开了一种通常具有第一电路和第二电路的装置。 第一电路可以被配置为响应于索引值产生（i）多个第一码位，并且响应于索引值，产生多个第一中间位。 可以与第一中间位并行地生成第一码位。 第二电路可以被配置为响应于（i）索引值，（ii）第一码位和（iii）第一中间位的全部产生多个第二码位。 第一码位和第二码位的组合通常形成多个正交码中的一个。

公开(公告)号：US20120324195A1

公开(公告)日：2012-12-20

申请号：US13159653

申请日：2011-06-14

申请人： Alexander Rabinovitch ,  Eliahou Arviv ,  Ido Gazit ,  Leonid Dubrovin

发明人： Alexander Rabinovitch ,  Eliahou Arviv ,  Ido Gazit ,  Leonid Dubrovin

IPC分类号： G06F12/02

CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6028

摘要： An apparatus generally having a cache memory and a circuit is disclosed. The circuit may be configured to (i) parse a single first command received from a processor into a first address and a first value and (ii) allocate a first one of a plurality of lines in the cache memory to a buffer in response to the first command. The first line (a) is generally associated with the first address and (b) may have a plurality of first words. The circuit may be further configured to (iii) preset each of the first words in the first line to the first value.

摘要翻译： 公开了一种通常具有高速缓冲存储器和电路的装置。 电路可以被配置为（i）将从处理器接收的单个第一命令解析为第一地址和第一值，并且（ii）响应于所述缓冲器将高速缓冲存储器中的多行中的第一行分配给缓冲器 第一个命令。 第一行（a）通常与第一地址相关联，并且（b）可以具有多个第一个单词。 该电路还可以被配置为（iii）将第一行中的每个第一个字预设为第一个值。

公开(公告)号：US20110058619A1

公开(公告)日：2011-03-10

申请号：US12555025

申请日：2009-09-08

申请人： Eliahou Arviv ,  Daniel Briker ,  Yitzhak Isac Casapu

发明人： Eliahou Arviv ,  Daniel Briker ,  Yitzhak Isac Casapu

IPC分类号： H04B7/02

CPC分类号： H04B7/0617 ,  H04B7/0413 ,  H04L5/0023 ,  H04L25/0244 ,  H04L2025/03414

摘要： In one embodiment, a method for signal processing is provided that uses an improved inversion to mitigate the imprecision introduced by fast approximate methods for division. An input signal is received and processed to generate a matrix M. The matrix M is inverted to generate an inverted matrix M−1. Matrix M is inverted by (i) decomposing the matrix M into a plurality of first sub-matrices, (ii) generating, based on the first sub-matrices and without any division operations, numerators for a plurality of second sub-matrices of the inverted matrix M−1, (iii) generating, based on the first sub-matrices and without any division operations, denominators for the second sub-matrices, and (iv) generating the second sub-matrices based on the numerators and denominators. The inverted matrix M−1 is processed to generate an output signal. Accordingly, a reduction in noise level from inaccuracy in division is achieved, and computational complexity is reduced.

摘要翻译： 在一个实施例中，提供了一种用于信号处理的方法，其使用改进的反演来减轻由快速近似分割方法引入的不精确性。 接收并处理输入信号以产生矩阵M.矩阵M被反相以产生反相矩阵M-1。 矩阵M通过（i）将矩阵M分解为多个第一子矩阵来反转，（ii）基于第一子矩阵并且没有任何除法运算，生成多个第一子矩阵的多个第二子矩阵的分子 反向矩阵M-1，（iii）基于第一子矩阵并且没有任何除法运算，生成用于第二子矩阵的分母，以及（iv）基于分子和分母产生第二子矩阵。 处理反相矩阵M-1以产生输出信号。 因此，实现了从划分不准确的噪声水平的降低，并且降低了计算复杂度。

公开(公告)号：US20080298334A1

公开(公告)日：2008-12-04

申请号：US11756152

申请日：2007-05-31

申请人： Eliahou Arviv ,  Simon Issakov ,  Rafael Carmon

发明人： Eliahou Arviv ,  Simon Issakov ,  Rafael Carmon

IPC分类号： H04Q7/28

CPC分类号： H04L1/0048 ,  H04B1/707 ,  H04J13/0044

摘要： In one embodiment, a method for determining whether an encoded message in a shared channel is not intended for a communications device. The method includes: (a) decoding the message to recover a multi-bit codeword; (b) determining whether the codeword is valid or invalid, wherein, if the codeword is determined to be invalid, then the encoded message is not intended for the communications device; and (c) if the codeword is determined to be valid, then performing one or more other steps of the method to determine whether the encoded message in the shared channel is not intended for the communications device.

摘要翻译： 在一个实施例中，一种用于确定共享信道中的编码消息是否不用于通信设备的方法。 该方法包括：（a）对消息进行解码以恢复多比特码字; （b）确定码字是有效还是无效，其中，如果所述码字被确定为无效，则所述编码消息不是针对所述通信设备的; 以及（c）如果所述码字被确定为有效，则执行所述方法的一个或多个其他步骤以确定所述共享信道中的编码消息是否不是针对所述通信设备。

公开(公告)号：US08571090B2

公开(公告)日：2013-10-29

申请号：US13494076

申请日：2012-06-12

申请人： Eliahou Arviv ,  Daniel Briker ,  Gennady Zilberman

发明人： Eliahou Arviv ,  Daniel Briker ,  Gennady Zilberman

IPC分类号： H04B1/00

CPC分类号： H04B1/7075 ,  H04B2001/70935

摘要： In one embodiment, a method for demodulating and searching for a preamble signal containing a complex phasor signal is disclosed. The complex phasor is demodulated using a phasor-rotated fast transformer. A received signal is correlated with a spreading code to produce a correlated signal. The correlated signal is coherently accumulated to produce a coherently accumulated signal. A first phasor-rotated signal transformation is performed on a real component of the coherently accumulated signal, and a second phasor-rotated signal transformation is performed on an imaginary component of the coherently accumulated signal. Finally, the signal power of the transformed real and imaginary components of the coherently accumulated signal is determined.

摘要翻译： 在一个实施例中，公开了一种用于解调和搜索包含复相量信号的前同步信号的方法。 使用相量旋转的快速变压器对复相量进行解调。 接收到的信号与扩展码相关以产生相关信号。 相关信号被相干累积以产生相干累积信号。 对相干累加信号的实分量执行第一相量旋转信号变换，并对相干累加信号的虚分量执行第二相量旋转信号变换。 最后，确定相干累加信号的变换的实分量和虚分量的信号功率。