公开(公告)号：US07010451B2

公开(公告)日：2006-03-07

申请号：US10417640

申请日：2003-04-17

申请人： Michael J. Dorough ,  Robert M. Gravelle ,  Sergey A. Velichko

发明人： Michael J. Dorough ,  Robert M. Gravelle ,  Sergey A. Velichko

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： G01R31/2894 ,  G01R31/2831

摘要： Methods, systems, and apparatuses provide dynamic creation and modification of wafer test maps. Test plans are defined for a testing session of a wafer lot. The test plan is associated with a number of seed map patterns. During a wafer lot testing session, test results are dynamically obtained and examined at run-time of a test. Moreover, the seed map patterns are overlaid on the test sites defined in the test plan. If the test result statistics are outside of defined threshold tolerance levels, then a new wafer test map is created or modified at run-time, according to corresponding seed map patterns. If seed map patterns are within the intersection of valid test sites, then seed map patterns are created at run-time.

摘要翻译： 方法，系统和装置提供晶片测试图的动态创建和修改。 测试计划是针对晶圆批次的测试会议定义的。 测试计划与许多种子图模式相关联。 在晶圆批测试期间，测试结果在测试运行时动态获取并进行检查。 此外，种子地图模式覆盖在测试计划中定义的测试站点上。 如果测试结果统计信息超出定义的阈值容限级别，则根据相应的种子图模式，在运行时创建或修改新的晶圆测试图。 如果种子地图模式位于有效测试站点的交叉点内，则在运行时创建种子地图模式。

公开(公告)号：US6140692A

公开(公告)日：2000-10-31

申请号：US865282

申请日：1997-05-29

申请人： Joseph C. Sher ,  Robert M. Gravelle

发明人： Joseph C. Sher ,  Robert M. Gravelle

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

摘要翻译： 在第一导电类型的硅衬底上形成改进的抗熔丝结构。 反熔丝具有形成在基板的表面上的第一导电层，形成在第一导电层上的电介质层和形成在电介质层上的第二导电层。 第二导电层具有延伸超过衬底表面之上的电介质层的部分。 第三导电层与第二电介质层的该部分接触。 反熔丝还包括在第二导电层的与第三导电层接触的部分下方在硅衬底中形成的梯度掺杂分布的阱区。 阱区具有与第一导电类型相反的第二导电类型。

公开(公告)号：US06307249B1

公开(公告)日：2001-10-23

申请号：US09389521

申请日：1999-09-02

申请人： Joseph C. Sher ,  Robert M. Gravelle

发明人： Joseph C. Sher ,  Robert M. Gravelle

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

摘要翻译： 在第一导电类型的硅衬底上形成改进的抗熔丝结构。 抗熔丝具有形成在基板的表面上的第一导电层，形成在第一导电层上的电介质层和形成在电介质层上的第二导电层。 第二导电层具有延伸超过衬底表面之上的电介质层的部分。 第三导电层与第二电介质层的该部分接触。 反熔丝还包括在第二导电层的与第三导电层接触的部分下方在硅衬底中形成的梯度掺杂分布的阱区。 阱区具有与第一导电类型相反的第二导电类型。

公开(公告)号：US06242335B1

公开(公告)日：2001-06-05

申请号：US09389522

申请日：1999-09-02

申请人： Joseph C. Sher ,  Robert M. Gravelle

发明人： Joseph C. Sher ,  Robert M. Gravelle

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

摘要翻译： 在第一导电类型的硅衬底上形成改进的抗熔丝结构。 反熔丝具有形成在基板的表面上的第一导电层，形成在第一导电层上的电介质层和形成在电介质层上的第二导电层。 第二导电层具有延伸超过衬底表面之上的电介质层的部分。 第三导电层与第二电介质层的该部分接触。 反熔丝还包括在第二导电层的与第三导电层接触的部分下方在硅衬底中形成的梯度掺杂分布的阱区。 阱区具有与第一导电类型相反的第二导电类型。