公开(公告)号：US06756805B2

公开(公告)日：2004-06-29

申请号：US10295499

申请日：2002-11-15

申请人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

发明人： Joseph C. Sher ,  David D. Siek ,  Huy Thanh Vo ,  Nicholas Van Heel ,  Victor Wong ,  Hua Zheng

IPC分类号： G01R104

CPC分类号： G11C29/02 ,  G01R31/3004 ,  G11C5/145 ,  G11C5/146 ,  G11C29/021 ,  G11C29/028 ,  G11C29/12 ,  G11C29/12005 ,  G11C2029/5004

摘要： A voltage generating circuit for generating internal voltage for a packaged integrated circuit memory device, is controllable to provide incremental adjustments in the voltage for testing of the memory device. The voltage generating circuit permits internally generated voltages of the memory device, such as the substrate voltage Vbb, the DVC2 voltage, and the pumped voltage Vccp, to be controlled externally through the application of test signals via the conventional test function, in performing standard device tests such as the static refresh test, logic 1s and 0s margin testing, and the like for packaged memory devices. Also, programmable circuits including programmable logic devices, such as anti-fuses, are provided that are programmable to maintain the voltage at a magnitude to which it is adjusted.

公开(公告)号：US06229296B1

公开(公告)日：2001-05-08

申请号：US08840503

申请日：1997-04-21

申请人： Kevin G. Duesman ,  Joseph C. Sher ,  Daniel R. Loughmiller

发明人： Kevin G. Duesman ,  Joseph C. Sher ,  Daniel R. Loughmiller

IPC分类号： G01R3126

CPC分类号： G01R31/2884

摘要： A circuit for reading and forcing a voltage at a node of an integrated circuit. In one embodiment, the circuit comprises a pass element that has an output that is coupled to a pin of the integrated circuit. A reset circuit is coupled to the pass circuit and is operable to activate and reset the pass circuit. Finally, a pass control circuit is coupled to provide a signal to the pass circuit that drives the pass circuit when active to pass the voltage at the node to the pin. In one embodiment, the circuit further includes a scaler circuit that establishes a ratio between the voltage at the node and the voltage at the pin such that high voltages can be passed to or from the node by the pass element.

摘要翻译： 用于读取和强制集成电路节点处的电压的电路。 在一个实施例中，电路包括通过元件，其具有耦合到集成电路的引脚的输出。 复位电路耦合到通路电路并且可操作以激活和复位通路电路。 最后，通路控制电路被耦合以向有助于将节点处的电压传递到引脚的通路电路提供一个驱动通路的信号。 在一个实施例中，电路还包括缩放器电路，其建立节点处的电压与引脚处的电压之间的比率，使得高电压可以通过传递元件传递到节点或从节点传递到节点。

公开(公告)号：US06169704A

公开(公告)日：2001-01-02

申请号：US09081983

申请日：1998-05-20

申请人： Joseph C. Sher

发明人： Joseph C. Sher

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/4076

摘要： A clock generator which provides a stable output clock signal based on an input clock signal. The clock generator provides a leading edge of an output clock signal in response to a leading edge of an input clock signal. The trailing edge of the output signal is conditioned on feedback of the leading edge output clock signal with the trailing edge of the input clock signal.

摘要翻译： 时钟发生器，其基于输入时钟信号提供稳定的输出时钟信号。 响应于输入时钟信号的前沿，时钟发生器提供输出时钟信号的前沿。 输出信号的后沿根据前沿输出时钟信号与输入时钟信号的后沿的反馈进行调节。

公开(公告)号：US6140692A

公开(公告)日：2000-10-31

申请号：US865282

申请日：1997-05-29

申请人： Joseph C. Sher ,  Robert M. Gravelle

发明人： Joseph C. Sher ,  Robert M. Gravelle

IPC分类号： H01L23/525 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of the substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

摘要翻译： 在第一导电类型的硅衬底上形成改进的抗熔丝结构。 反熔丝具有形成在基板的表面上的第一导电层，形成在第一导电层上的电介质层和形成在电介质层上的第二导电层。 第二导电层具有延伸超过衬底表面之上的电介质层的部分。 第三导电层与第二电介质层的该部分接触。 反熔丝还包括在第二导电层的与第三导电层接触的部分下方在硅衬底中形成的梯度掺杂分布的阱区。 阱区具有与第一导电类型相反的第二导电类型。

公开(公告)号：US6117696A

公开(公告)日：2000-09-12

申请号：US31934

申请日：1998-02-27

申请人： Daniel R. Loughmiller ,  Joseph C. Sher ,  Kevin G. Duesman

发明人： Daniel R. Loughmiller ,  Joseph C. Sher ,  Kevin G. Duesman

IPC分类号： G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2884

摘要： A circuit (10) for reading a voltage at a voltage source (14) of an integrated circuit (12). In one embodiment, the circuit (110) comprises a pass circuit (118) that has an input coupled to the node (114) of the integrated circuit (12). The circuit (110) provides a measurement of the voltage at the node (114) as an output to a pin (116). A reset circuit (122) is coupled to the pass circuit (118) and is operable to activate and reset the pass circuit (118). Finally, a pass control circuit (120) is coupled to provide an output signal to the pass circuit (118) that drives the pass circuit (118) when active to pass the voltage at the node (114) to the pin (116).

摘要翻译： 一种用于读取集成电路（12）的电压源（14）处的电压的电路（10）。 在一个实施例中，电路（110）包括通路电路（118），其具有耦合到集成电路（12）的节点（114）的输入端。 电路（110）提供节点（114）处的电压的测量作为针（116）的输出。 复位电路（122）耦合到通过电路（118）并且可操作以激活和复位通过电路（118）。 最后，当激活以将节点（114）处的电压传递到引脚（116）时，通过控制电路（120）被耦合以向传递电路（118）提供驱动通过电路（118）的输出信号。

公开(公告)号：US6069492A

公开(公告)日：2000-05-30

申请号：US925376

申请日：1997-09-08

申请人： Joseph C. Sher ,  Manny K. F. Ma

发明人： Joseph C. Sher ,  Manny K. F. Ma

IPC分类号： H03K19/003 ,  H03K19/0185 ,  H03K17/0185

CPC分类号： H03K19/018521 ,  H03K19/00384

摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.

摘要翻译： 电压补偿CMOS输入缓冲器将输入TTL信号转换为CMOS逻辑电平，并通过使用n沟道晶体管来补偿变化的电源电压，从而将p沟道对的有效尺寸比改变成组成输入反相器的n沟道晶体管。 补偿晶体管可以以增加的电源电压工作，以帮助n沟道输入反相器晶体管偏移通过增加电源电压而其跳变点将被增加的p沟道输入反相器晶体管。 随着电源电压的降低，补偿晶体管关闭，使输入逆变器返回原来的大小比例。 补偿晶体管的栅极通过两个二极管耦合到电源电压，以控制流过补偿晶体管的电流量。 与补偿晶体管串联的另外的跳变点晶体管的栅极耦合到输入信号以帮助稳定跳变点。 输出级反相器从输入反相器的输出提供CMOS逻辑电平。

公开(公告)号：US5949725A

公开(公告)日：1999-09-07

申请号：US915215

申请日：1997-08-20

申请人： Joseph C. Sher

发明人： Joseph C. Sher

IPC分类号： G11C5/14 ,  G11C29/46 ,  G11C7/00

CPC分类号： G11C29/46 ,  G11C5/145 ,  G11C5/147

摘要： In an integrated circuit including test circuitry for testing integrated circuit function, a programmable supervoltage circuit is described for enabling the test circuitry. The supervoltage circuit includes a reference circuit, a step-down circuit, a sensing circuit, and an output circuit. The reference circuit produces a reference voltage. The step-down circuit receives an input voltage and produces a stepped-down voltage. The sensing circuit is coupled with the reference and step-down circuits, receives the reference and stepped-down voltages, and produces a sense signal as a function of the relative values of the reference and stepped-down voltages. The output circuit is coupled with the sensing circuit, receives the sense signal, and produces a supervoltage output signal to enable the test circuitry. In a first embodiment, a programmable selection circuit is coupled with and selectively shunts one or more circuit elements in the step-down circuit to adjust the value of the stepped-down voltage relative to the input voltage. In a second embodiment, the selection circuit is coupled with and selectively shunts one or more circuit elements in the reference circuit to adjust the value of the reference voltage. In a third embodiment, the step-down circuit receives the input voltage at a selected one of a plurality of input terminals and produces a corresponding stepped-down voltage.

摘要翻译： 在包括用于测试集成电路功能的测试电路的集成电路中，描述了一个可编程超级电路，用于启用测试电路。 超级电路包括参考电路，降压电路，感测电路和输出电路。 参考电路产生参考电压。 降压电路接收输入电压并产生降压电压。 感测电路与参考和降压电路耦合，接收参考电压和降压电压，并产生作为参考电压和降压电压的相对值的函数的感测信号。 输出电路与感测电路耦合，接收感测信号，并产生超电压输出信号以使测试电路能够使用。 在第一实施例中，可编程选择电路与降压电路中的一个或多个电路元件耦合并选择性地分流，以相对于输入电压调节降压电压的值。 在第二实施例中，选择电路与参考电路中的一个或多个电路元件耦合并选择性地分流以调整参考电压的值。 在第三实施例中，降压电路在多个输入端子中选择的一个接收输入电压，并产生相应的降压电压。

公开(公告)号：US5896041A

公开(公告)日：1999-04-20

申请号：US654338

申请日：1996-05-28

申请人： Joseph C. Sher ,  Eric J. Smith

发明人： Joseph C. Sher ,  Eric J. Smith

IPC分类号： G11C29/04 ,  G11C17/18 ,  H01L23/525 ,  H01H85/00

CPC分类号： G11C17/18 ,  H01L2924/0002

摘要： A programming circuit for an anti-fuse utilizes a boot circuit that charges a capacitor to the supply voltage during a non-programming period. Anti-fuse is to be programmed, the plate of the capacitor to which the supply voltage has been applied is switched to 0 volts, thereby causing the other plate of the capacitor to output a negative voltage. This negative voltage is switched to one plate of an anti-fuse, and the other plate of the anti-fuse receives a positive voltage from an external source. A voltage is thereby applied across the anti-fuse that is greater than any voltage applied to any node of the integrated circuit.

摘要翻译： 用于反熔丝的编程电路利用在非编程周期期间将电容器充电到电源电压的引导电路。 要对防熔丝进行编程，将施加了电源电压的电容器的电压切换到0伏，从而使电容器的另一个电极输出负电压。 该负电压切换到一个反熔丝板，反熔丝的另一个板从外部电源接收正电压。 因此，跨过反熔丝施加的电压大于施加到集成电路的任何节点的任何电压。

公开(公告)号：US5848010A

公开(公告)日：1998-12-08

申请号：US892605

申请日：1997-07-14

申请人： Joseph C. Sher

发明人： Joseph C. Sher

IPC分类号： G11C17/18 ,  G11C29/02 ,  G11C13/00

CPC分类号： G11C17/18 ,  G11C29/02

摘要： A test circuit for stress testing antifuses before programming. The test circuit provides a voltage to an antifuse detection circuit during antifuse stress testing. In one embodiment, the provided voltage is externally received at a probe pad. In another embodiment, the test circuit controls a voltage generating circuit output voltage from a normal operating voltage to a stress voltage, such as by shifting the ground reference for the voltage generating circuit. The stress voltage can be varied as needed for a particular test setup and/or for different batches of antifuse circuits. Since the stress voltage is independent of the power supply voltage VCC, antifuse stressing can be concurrent with other pre-fuse tests, obviating the need for a dedicated antifuse stress test and reducing test time.

公开(公告)号：US5841714A

公开(公告)日：1998-11-24

申请号：US734504

申请日：1996-10-21

申请人： Joseph C. Sher ,  Todd A. Merritt

发明人： Joseph C. Sher ,  Todd A. Merritt

IPC分类号： G11C11/401 ,  G01R31/28 ,  G01R31/317 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C7/00

CPC分类号： G01R31/31701 ,  G11C29/46

摘要： A supervoltage circuit has been described which uses a resistor divider as an input stage. The resistor divider decreases the dependancy of the supervoltage trip point on transistor threshold voltages (Vt). The stability of supervoltage trip point is significantly increased over traditional supervoltage circuits using diode connected transistors as an input stage. The supervoltage circuit can be included in any integrated circuit including memory devices.

摘要翻译： 已经描述了使用电阻分压器作为输入级的超压电路。 电阻分压器降低了超级电压跳变点对晶体管阈值电压（Vt）的依赖性。 与使用二极管连接的晶体管作为输入级的传统超压电路相比，超级电压跳变点的稳定性显着提高。 超级电路可以包括在包括存储器件的任何集成电路中。