Delay circuit with reset-based forward path static delay
    2.
    发明授权
    Delay circuit with reset-based forward path static delay 有权
    具有基于复位的正向路径静态延迟的延迟电路

    公开(公告)号:US07276947B2

    公开(公告)日:2007-10-02

    申请号:US11493872

    申请日:2006-07-26

    IPC分类号: H03L7/00

    CPC分类号: H03L7/0814 G11C7/22 G11C7/222

    摘要: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

    摘要翻译: 延迟锁定环电路及其操作方法。 所述延迟锁定环电路包括具有可变延迟部分和静态延迟部分的前向延迟路径,其中所述静态延迟部分包括静态延迟元件,用于产生响应于输出信号的反馈信号的反馈路径,以及相位检测器 用于比较输入信号的相位和反馈信号的相位,并用于产生用于控制由可变延迟部分提供的延迟量的可变控制信号,其中静态延迟元件响应于指示的静态控制信号而被激活 的可变延迟部分不能将输出信号锁定到输入信号。 由于摘要规则,本摘要不应用于解释权利要求。

    Delay circuit with reset-based forward path static delay

    公开(公告)号:US20060038597A1

    公开(公告)日:2006-02-23

    申请号:US10922326

    申请日:2004-08-20

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0814 G11C7/22 G11C7/222

    摘要: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

    Delay circuit with reset-based forward path static delay
    5.
    发明授权
    Delay circuit with reset-based forward path static delay 有权
    具有基于复位的正向路径静态延迟的延迟电路

    公开(公告)号:US07126393B2

    公开(公告)日:2006-10-24

    申请号:US10922326

    申请日:2004-08-20

    IPC分类号: H03L7/00

    CPC分类号: H03L7/0814 G11C7/22 G11C7/222

    摘要: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.

    摘要翻译: 延迟锁定环电路及其操作方法。 所述延迟锁定环电路包括具有可变延迟部分和静态延迟部分的前向延迟路径,其中所述静态延迟部分包括静态延迟元件,用于产生响应于输出信号的反馈信号的反馈路径,以及相位检测器 用于比较输入信号的相位和反馈信号的相位,并用于产生用于控制由可变延迟部分提供的延迟量的可变控制信号,其中静态延迟元件响应于指示的静态控制信号而被激活 的可变延迟部分不能将输出信号锁定到输入信号。 由于摘要规则,本摘要不应用于解释权利要求。

    Delay circuit with reset-based forward path static delay

    公开(公告)号:US20060261871A1

    公开(公告)日:2006-11-23

    申请号:US11493872

    申请日:2006-07-26

    IPC分类号: H03L7/06

    CPC分类号: H03L7/0814 G11C7/22 G11C7/222

    摘要: A delay locked loop circuit and method of operating the same. The delay locked loop circuit comprises a forward delay path having a variable delay portion and a static delay portion, wherein the static delay portion includes a static delay element, a feedback path for generating a feedback signal responsive to an output signal, and a phase detector for comparing the phase of an input signal and the phase of the feedback signal and for generating a variable control signal for controlling the amount of delay provided by the variable delay portion, wherein the static delay element is activated in response to a static control signal indicative of the variable delay portion being unable to lock the output signal to the input signal. Because of the rules governing Abstracts, this Abstract should not be used to construe the claims.