公开(公告)号：US07206959B1

公开(公告)日：2007-04-17

申请号：US10351061

申请日：2003-01-24

申请人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

发明人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

IPC分类号： G06F1/04

CPC分类号： G06F1/3203 ,  G06F1/08 ,  Y02D10/126

摘要： The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

摘要翻译： 响应于时钟信号的频率的变化来调整存储器系统的电源电压。 存储器系统测量从数据在存储器的输出到下一个时钟边沿的数据有效的时间，以确定时序值。 当时钟频率从第一频率变化到第二频率时，定时值从第一值变为第二值。 改变电源电压的大小，将定时值返回到第一个值。

公开(公告)号：US08004329B1

公开(公告)日：2011-08-23

申请号：US12661560

申请日：2010-03-19

申请人： Hsing-Chien Roy Liu ,  Wai Cheong Chan

发明人： Hsing-Chien Roy Liu ,  Wai Cheong Chan

IPC分类号： H03L7/00

CPC分类号： G06F1/28

摘要： An apparatus includes a delay line having multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal through the delay cells. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the delay line and to output sampled values. The delay line has (i) a finer resolution closer to a target tap and (ii) a coarser resolution farther away from the target tap on each side of the target tap. For example, taps nearer the target tap can be closer to each other in order to support the finer resolution, and taps farther from the target tap can be farther apart from each other in order to support the coarser resolution. The apparatus can further include an encoder configured to encode the sampled values in order to generate an encoded value.

摘要翻译： 一种装置包括具有多个串联耦合的延迟单元的延迟线。 延迟线被配置为接收输入信号并且通过延迟单元传播输入信号。 该装置还包括多个采样电路，其经配置以在延迟线中的不同抽头处采样输入信号并输出​​采样值。 延迟线具有（i）更接近目标抽头的更精细的分辨率，以及（ii）在目标抽头的每一侧远离目标抽头的较粗分辨率。 例如，靠近目标水龙头的水龙头可以彼此靠近，以支持更精细的分辨率，并且离目标水龙头更远的水龙头可以彼此距离更远，以便支持更粗糙的分辨率。 该装置还可以包括被配置为对采样值进行编码以便生成编码值的编码器。

公开(公告)号：US20070265944A1

公开(公告)日：2007-11-15

申请号：US10688425

申请日：2003-10-16

申请人： Nardo Catahan ,  Ying-Chieh Lan ,  Roy Liu ,  Joshua Roper

发明人： Nardo Catahan ,  Ying-Chieh Lan ,  Roy Liu ,  Joshua Roper

IPC分类号： G07F19/00

CPC分类号： G06Q30/04 ,  G06Q40/12

摘要： Embodiments of the invention provide methods and data structures for the effective and efficient synchronization or inter-exchange of invoice information between business applications employing disparate DOFs. For one embodiment, a DOF is provided that allows for relationships between entities, also referred to as invoices, to be modeled as attributes of an entity and for customization of the DOF in a manner that facilitates upgrading of the DOF. For one embodiment, the invoice DOF is provided in a common software language such as XML. For one embodiment, invoice information from each of several business applications is translated to a common DOF. The invoice information, in the common DOF, is then inter-exchanged among the several business applications. Each application has only to translate the invoice information from the common DOF to the application-specific DOF of the respective business application.

摘要翻译： 本发明的实施例提供用于在使用不同DOF的业务应用之间有效且有效地同步或交换发票信息的方法和数据结构。 对于一个实施例，提供允许实体之间的关系（也称为发票）被建模为实体的属性并且以便于DOF的升级的方式自定义DOF的DOF。 对于一个实施例，发票DOF以诸如XML的通用软件语言提供。 对于一个实施例，来自几个业务应用程序中的每一个的发票信息被转换为常见的自由度。 然后，在多个商业应用程序中，通用DOF中的发票信息进行交互。 每个应用程序只需将发票信息从常规DOF转换为相应业务应用程序的特定于应用程序的DOF。

公开(公告)号：US07069461B1

公开(公告)日：2006-06-27

申请号：US10351056

申请日：2003-01-24

申请人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

发明人： Wai Cheong Chan ,  James Thomas Doyle ,  Pavel Poplevine ,  Murali Krishna Varadarajula ,  Hsing-Chien Roy Liu ,  Gordon Mortensen

IPC分类号： G06F1/04

CPC分类号： G11C5/14 ,  G11C7/1072 ,  G11C11/4074

摘要： The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

摘要翻译： 响应于时钟信号的频率的变化来调整存储器系统的电源电压。 存储器系统测量从数据在存储器的输出到下一个时钟边沿的数据有效的时间，以确定时序值。 当时钟频率从第一频率变化到第二频率时，定时值从第一值变为第二值。 改变电源电压的大小，将定时值返回到第一个值。