利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

3 条记录 (耗时 0.01 秒)

    Edge accelerated sense amplifier flip-flop with high fanout drive capability
    3.
    发明授权
    Edge accelerated sense amplifier flip-flop with high fanout drive capability 有权
    边缘加速读出放大器触发器，具有高扇出驱动能力

    公开(公告)号：US06924683B1

    公开(公告)日：2005-08-02

    申请号：US10741761

    申请日：2003-12-19

    申请人： Russell Hayter

    发明人： Russell Hayter

    IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K3/037 ,  H03K3/12

    CPC分类号： H03K3/356182 ,  H03K3/012 ,  H03K3/356139 ,  H03K3/356191

    摘要： Flip-flop devices provide fast clock-to-Q timing that exploits the pulsed nature of outputs generated by a clocked sense amplifier. These flip-flop devices include an output stage, which has a PMOS pull-up transistor and an NMOS pull-down transistor therein, and a clocked sense amplifier at an input stage. The clocked sense amplifier is configured to generate first and second data output signals (/SET and /RESET). These data output signals are provided to a signal edge acceleration stage. This signal edge acceleration stage is configured to generate the pull-up and pull-down control pulses in response to the first and second data output signals, respectively. This leading edge acceleration stage includes a pull-up buffer having an odd (even) number of inverters therein that are skewed to accelerate the leading edge of the pull-up control pulse relative to a trailing edge of the pull-up control pulse. The leading edge acceleration stage also includes a pull-down buffer having an even (odd) number of inverters therein that are skewed to accelerate the leading edge of the pull-down control pulse relative to a trailing edge of the pull-down control pulse. Accordingly, the pull-up buffer accelerates the clock-to-Q timing when driving Q high and the pull-down buffer accelerates the clock-to-Q timing when driving Q low.

    摘要翻译： 触发器器件提供快速的时钟到Q时序，利用时钟读出放大器产生的输出的脉冲特性。 这些触发器装置包括其中具有PMOS上拉晶体管和NMOS下拉晶体管的输出级和在输入级的时钟感测放大器。 时钟读出放大器被配置为产生第一和第二数据输出信号（/ SET和/ RESET）。 这些数据输出信号被提供给信号边缘加速阶段。 该信号边缘加速级被配置为分别响应于第一和第二数据输出信号产生上拉和下拉控制脉冲。 该前沿加速级包括其中具有奇数（偶数）数量的反相器的上拉缓冲器，其被倾斜以加速上拉控制脉冲的前沿相对于上拉控制脉冲的后沿。 前沿加速阶段还包括其中具有偶数（奇数）数量的反相器的下拉缓冲器，其被倾斜以相对于下拉控制脉冲的后沿加速下拉控制脉冲的前沿。 因此，当驱动Q高电平时，上拉缓冲器加速时钟到Q定时，并且当驱动Q低电平时，下拉缓冲器加速时钟到Q定时。