公开(公告)号：US20240427705A1

公开(公告)日：2024-12-26

申请号：US18753378

申请日：2024-06-25

Applicant: SEMIBRAIN INC.

Inventor： Younghee Jeon ,  Daewung Kim ,  Seung-Hwan Song

IPC: G06F12/0875

Abstract: The present invention discloses a hardware computing device comprising a non-transitory computer-readable storage medium configured to store one or more computer-executable instructions; a host processing unit configured to determine whether and how artificial neural network model-based computations should be assigned to a second processing unit; and a hardware accelerator configured to execute one or more artificial neural network computations assigned by the host processing unit, wherein the hardware accelerator sequentially executes instructions in an instruction stream with a single instruction fetch by detecting a successive address of a next instruction.

公开(公告)号：US20230154523A1

公开(公告)日：2023-05-18

申请号：US17526567

申请日：2021-11-15

Applicant: SEMIBRAIN INC.

Inventor： Seung-Hwan Song

IPC: G11C11/4074 ,  G11C11/4099 ,  G11C11/4096 ,  G11C5/14

CPC classification number: G11C11/4074 ,  G11C11/4099 ,  G11C11/4096 ,  G11C5/14

Abstract: A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.

公开(公告)号：US20240274195A1

公开(公告)日：2024-08-15

申请号：US18439744

申请日：2024-02-12

Applicant: SEMIBRAIN INC.

Inventor： Dong-Hyuk Chae

IPC: G11C16/04 ,  G11C5/06 ,  H01L29/788 ,  H10B41/10

CPC classification number: G11C16/0483 ,  G11C5/063 ,  H01L29/7889 ,  H10B41/10

Abstract: The present invention discloses an embedded flash memory cell array structure characterized by improving integration by reducing the pitch of the cell layout in the row direction by sharing a source or drain with an adjacent control gate transistor.

公开(公告)号：US11862227B2

公开(公告)日：2024-01-02

申请号：US17526567

申请日：2021-11-15

Applicant: SEMIBRAIN INC.

Inventor： Seung-Hwan Song

IPC: G11C11/40 ,  G11C11/4074 ,  G11C5/14 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4074 ,  G11C5/14 ,  G11C11/4096 ,  G11C11/4099

Abstract: A driver circuit for operating a memory cell, adapted to be coupled to at least one memory cell through a respective output node, said driver circuit including: a first circuit for supplying the memory cell with a first read reference voltage through the output node; a second circuit for supplying the memory cell with a second read reference voltage through the output node; and a third circuit for controlling an operation of the second circuit, wherein a range of the second read reference voltage at the output node is wider than a range of the first read reference voltage at the output node during a read operation on the memory cell.