公开(公告)号：US08557673B1

公开(公告)日：2013-10-15

申请号：US13476251

申请日：2012-05-21

申请人： Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Cheng-Yeh Hsu ,  Chung-Lin Huang

IPC分类号： H01L21/02

CPC分类号： H01L28/91

摘要： A manufacturing method of a capacitor structure is provided, which includes the steps of: on a substrate having a first oxide layer, (a) forming a first suspension layer on the first oxide layer; (b) forming a first shallow trench into the first oxide layer above the substrate; (c) forming a second oxide layer filling the first shallow trench; (d) forming a second suspension layer on the second oxide layer; (e) forming a second shallow trench through the second suspension layer into the second oxide layer above the first suspension layer; (f) forming at least one deep trench on the bottom surface of the second shallow trench through the second and the first oxide layers, (g) forming an electrode layer on the inner surface of the deep trench; and (h) removing the first and second oxide layers through the trench openings in the first and the second suspension layers.

摘要翻译： 提供一种电容器结构的制造方法，其包括以下步骤：在具有第一氧化物层的衬底上，（a）在第一氧化物层上形成第一悬浮层; （b）在衬底上方的第一氧化物层中形成第一浅沟槽; （c）形成填充所述第一浅沟槽的第二氧化物层; （d）在第二氧化物层上形成第二悬浮层; （e）通过所述第二悬浮层形成穿过所述第一悬浮层上方的所述第二氧化物层的第二浅沟槽; （f）通过第二和第一氧化物层在第二浅沟槽的底表面上形成至少一个深沟槽，（g）在深沟槽的内表面上形成电极层; 和（h）通过第一和第二悬浮层中的沟槽开口去除第一和第二氧化物层。

公开(公告)号：US07960241B2

公开(公告)日：2011-06-14

申请号：US12698322

申请日：2010-02-02

申请人： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L28/90

摘要： A manufacturing method for double-side capacitor of stack DRAM has steps of: forming a sacrificial structure in the isolating trench and the capacitor trenches; forming a first covering layer and a second covering layer on the sacrificial structure; modifying a part of the second covering layer; removing the un-modified second covering layer and the first covering layer to expose the sacrificial structure; removing the exposed part of the sacrificial structure to expose the electrode layer; removing the exposed electrode layer to expose the oxide layer; and removing the oxide layer and sacrificial structure to form the double-side capacitors.

摘要翻译： 堆叠DRAM的双面电容器的制造方法具有以下步骤：在隔离沟槽和电容器沟槽中形成牺牲结构; 在所述牺牲结构上形成第一覆盖层和第二覆盖层; 修改第二覆盖层的一部分; 去除未改性的第二覆盖层和第一覆盖层以暴露牺牲结构; 去除所述牺牲结构的暴露部分以暴露所述电极层; 去除暴露的电极层以暴露氧化物层; 并去除氧化物层和牺牲结构以形成双面电容器。

公开(公告)号：US07868377B2

公开(公告)日：2011-01-11

申请号：US11927616

申请日：2007-10-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅晶体管的选通栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US20070170400A1

公开(公告)日：2007-07-26

申请号：US11336142

申请日：2006-01-20

申请人： Chung-Cheng Chang ,  Shin-Bin Huang

发明人： Chung-Cheng Chang ,  Shin-Bin Huang

IPC分类号： H01B1/12

CPC分类号： H01B1/08

摘要： An indium oxide based material containing carbon, and a method for preparing the same are provided. In such a method, the carbon is added to the indium oxide based material film so that the electrical resistivity of the indium oxide based material film is decreased, and the light transmittance of the indium oxide based material in the shorter wavelength range is increased, and also the light can transmit through such a material over a broader short wavelength range. The indium oxide based material prepared by the method of the present invention has higher electrical conductivity and higher light transmittance in comparison with the conventional one without adding carbon.

摘要翻译： 提供含有碳的氧化铟基材料及其制备方法。 在这种方法中，将碳添加到氧化铟基材料膜中，使得氧化铟基材料膜的电阻率降低，并且氧化铟基材料在较短波长范围内的透光率增加，并且 光也可以在较宽的短波长范围内透过这种材料。 通过本发明的方法制备的氧化铟基材料与不添加碳的现有技术相比，具有更高的导电性和更高的透光率。

公开(公告)号：US08330198B2

公开(公告)日：2012-12-11

申请号：US12758252

申请日：2010-04-12

申请人： Shin Bin Huang ,  Chung-Lin Huang ,  Ching-Nan Hsiao ,  Tzung Han Lee

发明人： Shin Bin Huang ,  Chung-Lin Huang ,  Ching-Nan Hsiao ,  Tzung Han Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/0259

摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

摘要翻译： 用于防止漏电的装置位于存储单元的晶体管和电容器之间。 用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。 用于防止漏电的装置具有至少两个p-n结。 用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。 通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

公开(公告)号：US08288224B2

公开(公告)日：2012-10-16

申请号：US12699399

申请日：2010-02-03

申请人： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Tzung-Han Lee ,  Chung-Lin Huang

IPC分类号： H01L21/8242

CPC分类号： H01L28/92

摘要： A method for manufacturing capacitor lower electrodes includes a dielectric layer, a first silicon nitride layer and a hard mask layer; partially etching the hard mask layer, the first silicon nitride layer and the dielectric layer to form a plurality of concave portions; depositing a second silicon nitride layer onto the hard mask layer and into the concave portions; partially etching the second silicon nitride layer, the hard mask layer and the dielectric layer to form a plurality of trenches; forming a capacitor lower electrode within each trench and partially etching the first silicon nitride layer, the second silicon nitride layer, the dielectric layer and the capacitor lower electrodes to form an etching area; and etching and removing the dielectric layer from the etching area, thereby a periphery of each capacitor lower electrode is surrounded and attached to by the second silicon nitride layer.

摘要翻译： 制造电容器下电极的方法包括电介质层，第一氮化硅层和硬掩模层; 部分地蚀刻硬掩模层，第一氮化硅层和电介质层以形成多个凹部; 在所述硬掩模层上沉积第二氮化硅层并进入所述凹部; 部分蚀刻第二氮化硅层，硬掩模层和电介质层以形成多个沟槽; 在每个沟槽内形成电容器下电极，并部分地蚀刻第一氮化硅层，第二氮化硅层，电介质层和电容器下电极以形成蚀刻区域; 并且从蚀刻区域蚀刻除去电介质层，由此每个电容器下电极的周围被第二氮化硅层包围并附着。

公开(公告)号：US20110127574A1

公开(公告)日：2011-06-02

申请号：US12758252

申请日：2010-04-12

申请人： SHIN BIN HUANG ,  CHUNG-LIN HUANG ,  CHING-NAN HSIAO ,  TZUNG HAN LEE

发明人： SHIN BIN HUANG ,  CHUNG-LIN HUANG ,  CHING-NAN HSIAO ,  TZUNG HAN LEE

IPC分类号： H01L27/108 ,  H01L27/06

CPC分类号： H01L27/0259

摘要： A device for preventing current-leakage is located between a transistor and a capacitor of a memory cell. The two terminals of the device for preventing current-leakage are respectively connected with a slave terminal of the transistor and an electric pole of the capacitor. The device for preventing current-leakage has at least two p-n junctions. The device for preventing current-leakage is a lateral silicon controlled rectifier, a diode for alternating current, or a silicon controlled rectifier. By utilizing the driving characteristic of the device for preventing current-leakage, electric charge stored in the capacitor hardly passes through the device for preventing current-leakage when the transistor is turned off to improve the current-leakage problem.

摘要翻译： 用于防止漏电的装置位于存储单元的晶体管和电容器之间。 用于防止漏电的装置的两个端子分别与晶体管的从端和电容器的电极连接。 用于防止漏电的装置具有至少两个p-n结。 用于防止漏电的装置是侧向可控硅整流器，用于交流电流的二极管或可控硅整流器。 通过利用用于防止漏电的装置的驱动特性，存储在电容器中的电荷几乎不会通过用于防止晶体管截止时漏电的装置，从而改善漏电问题。

公开(公告)号：US20110090617A1

公开(公告)日：2011-04-21

申请号：US12686399

申请日：2010-01-13

申请人： Shin-Bin Huang ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Chung-Lin Huang

IPC分类号： H01G4/005 ,  H01G4/00

CPC分类号： H01G4/33 ,  H01G4/005 ,  H01G4/228 ,  H01L23/50 ,  H01L27/10852 ,  H01L28/88 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a capacitor electrode. A stack structure is formed on a substrate, and the stack structure includes a first conductive layer, a first sacrificial layer, and a second sacrificial layer. The stack structure includes a first sidewall and a second sidewall facing the first sidewall. A conductive sidewall is formed on the first sidewall and the second sidewall to electrically connect the first conductive layer to the second conductive layer. Finally, the first and the second sacrificial layers are removed.

摘要翻译： 一种制造电容器电极的方法。 堆叠结构形成在衬底上，堆叠结构包括第一导电层，第一牺牲层和第二牺牲层。 堆叠结构包括第一侧壁和面向第一侧壁的第二侧壁。 导电侧壁形成在第一侧壁和第二侧壁上，以将第一导电层电连接到第二导电层。 最后，去除第一和第二牺牲层。

公开(公告)号：US20090032858A1

公开(公告)日：2009-02-05

申请号：US11927616

申请日：2007-10-29

申请人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

发明人： Shin-Bin Huang ,  Ching-Nan Hsiao ,  Chung-Lin Huang

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A flash memory is provided. The flash memory features of having the select gate transistors to include two different channel structures, which are a recessed channel structure and a horizontal channel. Because of the design of the recessed channel structure, the space between the gate conductor lines, which are for interconnecting the select gates of the select gate transistors arranged on the same column, can be shortened. Therefore, the integration of the flash memory can be increased; and the process window of the STI process can be increased as well. In addition, at least one depletion-mode select gate transistor is at one side of the memory cell string. The select gate transistor of the depletion-mode is always turned on.

摘要翻译： 提供闪存。 具有选择栅极晶体管的闪存特征包括两个不同的沟道结构，它们是凹陷沟道结构和水平沟道。 由于凹陷沟道结构的设计，可以缩短用于互连布置在同一列上的选择栅极晶体管的选择栅极的栅极导体线之间的空间。 因此，可以增加闪存的集成; 并且可以增加STI过程的处理窗口。 此外，至少一个耗尽型选择栅极晶体管位于存储单元串的一侧。 耗尽模式的选择栅晶体管总是导通。

公开(公告)号：US07462302B2

公开(公告)日：2008-12-09

申请号：US11336142

申请日：2006-01-20

申请人： Chung-Cheng Chang ,  Shin-Bin Huang

发明人： Chung-Cheng Chang ,  Shin-Bin Huang

IPC分类号： H01B1/08

CPC分类号： H01B1/08

摘要： An indium oxide based material containing carbon, and a method for preparing the same are provided. In such a method, the carbon is added to the indium oxide based material film so that the electrical resistivity of the indium oxide based material film is decreased, and the light transmittance of the indium oxide based material in the shorter wavelength range is increased, and also the light can transmit through such a material over a broader short wavelength range. The indium oxide based material prepared by the method of the present invention has higher electrical conductivity and higher light transmittance in comparison with the conventional one without adding carbon.

摘要翻译： 提供含有碳的氧化铟基材料及其制备方法。 在这种方法中，将碳添加到氧化铟基材料膜中，使得氧化铟基材料膜的电阻率降低，并且氧化铟基材料在较短波长范围内的透光率增加，并且 光也可以在较宽的短波长范围内透过这种材料。 通过本发明的方法制备的氧化铟基材料与不添加碳的现有技术相比，具有更高的导电性和更高的透光率。