公开(公告)号：US07363396B2

公开(公告)日：2008-04-22

申请号：US11361344

申请日：2006-02-24

Applicant: Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

Inventor： Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

IPC: G06F13/12 ,  G06F3/00 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F13/387

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract translation: 具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。 第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。 第二RAM还被配置为存储来自至少两个引擎的I / O完成。 当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。 第一个处理器处理存储在第一个RAM中的I / O完成。 第二处理器处理存储在第二RAM中的I / O完成。

公开(公告)号：US07328334B2

公开(公告)日：2008-02-05

申请号：US10856162

申请日：2004-05-27

Applicant: Sam Su ,  Hossein Hashemi ,  Qing Xue

Inventor： Sam Su ,  Hossein Hashemi ,  Qing Xue

IPC: G06F15/177

CPC classification number: G06F9/4403 ,  G06F1/24

Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Abstract translation: 在一个实施例中，初始化扩展设备可以提供扩展的初始化时段，以使处理器在进入操作模式之前配置设备，例如专用集成电路（ASIC）。 该设备可以包括多个控制寄存器，其可以被配置为在响应于复位信号而开始的寄存器初始化时段中的默认设置。 复位信号还可以触发扩展定时器以对定时器延长的初始化周期进行倒计时。 在定时器延长的初始化时段期间，处理器可以将扩展控制信号（例如，扩展位）写入寄存器。 初始化扩展单元可以在定时器扩展初始化周期期间和/或当寄存器包含扩展控制信号时将设备维持在初始化模式。 处理器可以配置控制寄存器用于设备在进入操作模式时可以执行的一个或多个操作。

公开(公告)号：US07096296B2

公开(公告)日：2006-08-22

申请号：US10995456

申请日：2004-11-22

Applicant: Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

Inventor： Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

IPC: G06F13/24 ,  G06F13/32

CPC classification number: G06F13/28 ,  G06F13/387

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

公开(公告)号：US20060143341A1

公开(公告)日：2006-06-29

申请号：US11361344

申请日：2006-02-24

Applicant: Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

Inventor： Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

IPC: G06F13/38

CPC classification number: G06F13/28 ,  G06F13/387

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

公开(公告)号：US20050097240A1

公开(公告)日：2005-05-05

申请号：US10995456

申请日：2004-11-22

Applicant: Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

Inventor： Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

IPC: G06F13/12 ,  G06F13/14 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F13/387

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract translation: 具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。 第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。 第二RAM还被配置为存储来自至少两个引擎的I / O完成。 当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。 第一个处理器处理存储在第一个RAM中的I / O完成。 第二处理器处理存储在第二RAM中的I / O完成。

公开(公告)号：US6047339A

公开(公告)日：2000-04-04

申请号：US957856

申请日：1997-10-27

Applicant: Sam Su ,  Vi Chau ,  Dan Tarr

Inventor： Sam Su ,  Vi Chau ,  Dan Tarr

IPC: G06F13/12 ,  G06F5/14 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/4059

Abstract: A "virtual FIFO" system for use in buffering data between transacting buses that transfer data at different rates includes a memory device and a controller that partitions the memory device into multiple regions, each of which is configured to operate as a distinct data buffer.

Abstract translation: 用于在以不同速率传送数据的交易总线之间缓冲数据的“虚拟FIFO”系统包括将存储器设备分成多个区域的存储器设备和控制器，每个区域被配置为作为不同的数据缓冲器操作。

公开(公告)号：US06894935B2

公开(公告)日：2005-05-17

申请号：US10440855

申请日：2003-05-19

Applicant: Eric Peel ,  Qing Xue ,  Sam Su ,  Stephen Eugene Holness

Inventor： Eric Peel ,  Qing Xue ,  Sam Su ,  Stephen Eugene Holness

IPC: G11C7/10 ,  G11C7/22 ,  G11C16/04

CPC classification number: G11C7/1006 ,  G11C7/22

Abstract: The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths. Finally, in accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of memory devices having different bus widths and different data transfer timing.

Abstract translation: 本发明涉及一种用于在存储器件和集成电路之间传送数据的存储器数据接口，由此根据本发明的一个方面，存储器数据接口包括用于从存储器件中选择和归一化数据的数据选择器 在不同的数据传输定时操作，并且根据本发明的另一方面，存储器数据接口能够在存储器件和具有与存储器件不同的总线宽度的集成电路之间传送数据。 根据本发明的另一方面，存储器数据接口能够在集成电路和具有不同数据总线宽度的各种不同的存储器件之间传送数据。 最后，根据本发明的另一方面，存储器数据接口能够在集成电路和具有不同总线宽度和不同数据传输时序的各种存储器件之间传送数据。

公开(公告)号：US06829660B2

公开(公告)日：2004-12-07

申请号：US10316604

申请日：2002-12-10

Applicant: Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

Inventor： Michael Liu ,  Bradley Roach ,  Sam Su ,  Peter Fiacco

IPC: G06F1328

CPC classification number: G06F13/28 ,  G06F13/387

Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Abstract translation: 具有第一随机存取存储器（RAM），第二RAM，耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。 第一个RAM被配置为存储来自至少两个引擎的输入/输出（I / O）完成。 第二RAM还被配置为存储来自至少两个引擎的I / O完成。 当所有引擎都处于活动状态时，系统将I / O完成从引擎写入第一个和第二个RAM。 第一个处理器处理存储在第一个RAM中的I / O完成。 第二处理器处理存储在第二RAM中的I / O完成。

公开(公告)号：US06496514B2

公开(公告)日：2002-12-17

申请号：US09730149

申请日：2000-12-04

Applicant: Sam Su ,  David Baldwin ,  Qing Xue ,  Hossein Hashemi

Inventor： Sam Su ,  David Baldwin ,  Qing Xue ,  Hossein Hashemi

IPC: H04L1242

CPC classification number: H04L12/4625 ,  H04L12/403 ,  H04L12/42

Abstract: A hub port in a Fibre Channel loop for detecting and bypassing attached node ports in an OLD-PORT state is disclosed. The hub port includes a hub data source, a detect circuits, and an output control circuit. The hub data source supplies data to the hub port from a Fibre Channel loop. The detect circuit is configured to detect a valid non-Arbitrated Loop sequence from an attached node port indicating that the node port is in an OLD-PORT state. The output control circuit operates to bypass the node port from the loop when the valid non-Arbitrated Loop sequence is detected.

公开(公告)号：US20180334625A1

公开(公告)日：2018-11-22

申请号：US15902962

申请日：2018-02-22

Applicant: Sam Su

Inventor： Sam Su

IPC: C10J3/72 ,  C10J3/48 ,  C10B53/00 ,  B01D3/14

CPC classification number: C10J3/721 ,  B01D3/14 ,  B01D2257/302 ,  B01D2257/55 ,  C10B53/00 ,  C10J3/482 ,  C10J2300/093 ,  C10J2300/0959 ,  C10J2300/12 ,  C10J2300/1606 ,  C10J2300/1696

Abstract: In one aspect, a method for coal purification and gasification may include steps of heating the coal including various hydrocarbons and harmful substances such as sulfides, phosphates, etc. to 900 to 1200° C. in a coal gasifier; providing a reaction chamber with oxygen and connecting with the coal gasifier; the sulfides, phosphates, etc. in the gasified coal entering the reaction chamber from the coal gasifier and reacting with the oxygen therein; separating mixtures from the reaction chamber to collect hydrocarbons in its fluidized phase; heating the fluidized hydrocarbons; and providing oxygen to react with the gasified form of hydrocarbons to achieve a complete burning of the hydrocarbons.