Old-port node detection and hub port bypass

    公开(公告)号:US06496514B2

    公开(公告)日:2002-12-17

    申请号:US09730149

    申请日:2000-12-04

    CPC classification number: H04L12/4625 H04L12/403 H04L12/42

    Abstract: A hub port in a Fibre Channel loop for detecting and bypassing attached node ports in an OLD-PORT state is disclosed. The hub port includes a hub data source, a detect circuits, and an output control circuit. The hub data source supplies data to the hub port from a Fibre Channel loop. The detect circuit is configured to detect a valid non-Arbitrated Loop sequence from an attached node port indicating that the node port is in an OLD-PORT state. The output control circuit operates to bypass the node port from the loop when the valid non-Arbitrated Loop sequence is detected.

    Elastic bus interface data buffer
    2.
    发明授权
    Elastic bus interface data buffer 失效
    弹性总线接口数据缓冲

    公开(公告)号:US5838936A

    公开(公告)日:1998-11-17

    申请号:US813271

    申请日:1997-03-10

    Inventor: Vi Chau Sam Su Dan Tarr

    CPC classification number: G06F13/405 Y02B60/1228 Y02B60/1235

    Abstract: An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.

    Abstract translation: 弹性总线接口接收和注册外部数据传输信号,并产生一个始终从后续时钟周期开始的内部数据传输信号,无论外部数据传输信号的到达时间如何。 通过在流水线中采用多个数据输出寄存器并且仅使用内部数据传送信号,将数据馈送到总线,以确保几乎完整的时钟周期可用于建立时间以完成数据传输。 本发明可以使用仅使用简单的常规电路和仅需要最小芯片面积和功率的适中的工艺几何形状的高速总线来操作。

    Circuit for interfacing data busses
    3.
    发明授权
    Circuit for interfacing data busses 失效
    用于连接数据总线的电路

    公开(公告)号:US5555433A

    公开(公告)日:1996-09-10

    申请号:US259403

    申请日:1994-06-13

    CPC classification number: G06F13/364

    Abstract: A system for changing the source and destination devices of data transfers under software control. Default data transfers are made from numbered source devices to the same-numbered destination devices, the data requests being routed through multiplexers which pair, for example, source 1 with destination 1, source 2 with destination 2, etc. The multiplexer control signals originate in a register which is originally loaded with default control bits. However, in real time, the bits within the control register can be re-loaded to provide outputs other than the default values. Then, the data from a source can be directed to any one of the destination devices.

    Abstract translation: 用于在软件控制下更改数据传输的源和目标设备的系统。 默认数据传输是从编号的源设备到相同编号的目标设备,数据请求通过多路复用器进行路由,多路复用器与例如源1与目的地1,源2与目的地2配对等。多路复用器控制信号起源于 一个最初加载了默认控制位的寄存器。 然而,实际上,可以重新加载控制寄存器中的位以提供非默认值的输出。 然后,来自源的数据可以被引导到目的地设备中的任何一个。

    Memory data interface
    4.
    发明授权
    Memory data interface 有权
    内存数据接口

    公开(公告)号:US06894935B2

    公开(公告)日:2005-05-17

    申请号:US10440855

    申请日:2003-05-19

    CPC classification number: G11C7/1006 G11C7/22

    Abstract: The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths. Finally, in accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of memory devices having different bus widths and different data transfer timing.

    Abstract translation: 本发明涉及一种用于在存储器件和集成电路之间传送数据的存储器数据接口,由此根据本发明的一个方面,存储器数据接口包括用于从存储器件中选择和归一化数据的数据选择器 在不同的数据传输定时操作,并且根据本发明的另一方面,存储器数据接口能够在存储器件和具有与存储器件不同的总线宽度的集成电路之间传送数据。 根据本发明的另一方面,存储器数据接口能够在集成电路和具有不同数据总线宽度的各种不同的存储器件之间传送数据。 最后,根据本发明的另一方面,存储器数据接口能够在集成电路和具有不同总线宽度和不同数据传输时序的各种存储器件之间传送数据。

    Supercharge message exchanger
    5.
    发明授权
    Supercharge message exchanger 有权
    增压消息交换机

    公开(公告)号:US06829660B2

    公开(公告)日:2004-12-07

    申请号:US10316604

    申请日:2002-12-10

    CPC classification number: G06F13/28 G06F13/387

    Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

    Abstract translation: 具有第一随机存取存储器(RAM),第二RAM,耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。 第一个RAM被配置为存储来自至少两个引擎的输入/输出(I / O)完成。 第二RAM还被配置为存储来自至少两个引擎的I / O完成。 当所有引擎都处于活动状态时,系统将I / O完成从引擎写入第一个和第二个RAM。 第一个处理器处理存储在第一个RAM中的I / O完成。 第二处理器处理存储在第二RAM中的I / O完成。

    Supercharge message exchanger
    6.
    发明授权
    Supercharge message exchanger 有权
    增压消息交换机

    公开(公告)号:US07363396B2

    公开(公告)日:2008-04-22

    申请号:US11361344

    申请日:2006-02-24

    CPC classification number: G06F13/28 G06F13/387

    Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

    Abstract translation: 具有第一随机存取存储器(RAM),第二RAM,耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。 第一个RAM被配置为存储来自至少两个引擎的输入/输出(I / O)完成。 第二RAM还被配置为存储来自至少两个引擎的I / O完成。 当所有引擎都处于活动状态时,系统将I / O完成从引擎写入第一个和第二个RAM。 第一个处理器处理存储在第一个RAM中的I / O完成。 第二处理器处理存储在第二RAM中的I / O完成。

    Hardware initialization with or without processor intervention
    7.
    发明授权
    Hardware initialization with or without processor intervention 有权
    硬件初始化有或没有处理器干预

    公开(公告)号:US07328334B2

    公开(公告)日:2008-02-05

    申请号:US10856162

    申请日:2004-05-27

    CPC classification number: G06F9/4403 G06F1/24

    Abstract: In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

    Abstract translation: 在一个实施例中,初始化扩展设备可以提供扩展的初始化时段,以使处理器在进入操作模式之前配置设备,例如专用集成电路(ASIC)。 该设备可以包括多个控制寄存器,其可以被配置为在响应于复位信号而开始的寄存器初始化时段中的默认设置。 复位信号还可以触发扩展定时器以对定时器延长的初始化周期进行倒计时。 在定时器延长的初始化时段期间,处理器可以将扩展控制信号(例如,扩展位)写入寄存器。 初始化扩展单元可以在定时器扩展初始化周期期间和/或当寄存器包含扩展控制信号时将设备维持在初始化模式。 处理器可以配置控制寄存器用于设备在进入操作模式时可以执行的一个或多个操作。

    Supercharge message exchanger
    8.
    发明授权

    公开(公告)号:US07096296B2

    公开(公告)日:2006-08-22

    申请号:US10995456

    申请日:2004-11-22

    CPC classification number: G06F13/28 G06F13/387

    Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

    Supercharge message exchanger
    9.
    发明申请

    公开(公告)号:US20060143341A1

    公开(公告)日:2006-06-29

    申请号:US11361344

    申请日:2006-02-24

    CPC classification number: G06F13/28 G06F13/387

    Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

    Supercharge message exchanger
    10.
    发明申请
    Supercharge message exchanger 失效
    增压消息交换机

    公开(公告)号:US20050097240A1

    公开(公告)日:2005-05-05

    申请号:US10995456

    申请日:2004-11-22

    CPC classification number: G06F13/28 G06F13/387

    Abstract: A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

    Abstract translation: 具有第一随机存取存储器(RAM),第二RAM,耦合到第一RAM的第一处理器和耦合到第二RAM的第二处理器的系统。 第一个RAM被配置为存储来自至少两个引擎的输入/输出(I / O)完成。 第二RAM还被配置为存储来自至少两个引擎的I / O完成。 当所有引擎都处于活动状态时,系统将I / O完成从引擎写入第一个和第二个RAM。 第一个处理器处理存储在第一个RAM中的I / O完成。 第二处理器处理存储在第二RAM中的I / O完成。

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