公开(公告)号：US20060160354A1

公开(公告)日：2006-07-20

申请号：US11374848

申请日：2006-03-14

申请人： BeiChao Zhang ,  Chun Low ,  Hong Lee ,  Sang Loong ,  Qiang Guo

发明人： BeiChao Zhang ,  Chun Low ,  Hong Lee ,  Sang Loong ,  Qiang Guo

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

公开(公告)号：US20050090097A1

公开(公告)日：2005-04-28

申请号：US10692028

申请日：2003-10-23

申请人： Beichao Zhang ,  Chun Low ,  Hong Lee ,  Sang Loong ,  Giang Guo

发明人： Beichao Zhang ,  Chun Low ,  Hong Lee ,  Sang Loong ,  Giang Guo

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/76805 ,  H01L21/76814

摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

摘要翻译： 描述了一种用于提高半导体器件中的电迁移阻力的集成方法。 在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。 一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。 在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。 另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。 发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

公开(公告)号：US20050014294A1

公开(公告)日：2005-01-20

申请号：US10915670

申请日：2004-08-10

申请人： Ting Ang ,  Sang Loong ,  Shyue Quek ,  Jun Song

发明人： Ting Ang ,  Sang Loong ,  Shyue Quek ,  Jun Song

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/76

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。