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    Novel method of body contact for SOI MOSFET
    1.
    发明申请
    Novel method of body contact for SOI MOSFET 有权
    SOI MOSFET的体接触新方法

    公开(公告)号：US20050014294A1

    公开(公告)日：2005-01-20

    申请号：US10915670

    申请日：2004-08-10

    申请人： Ting Ang ,  Sang Loong ,  Shyue Quek ,  Jun Song

    发明人： Ting Ang ,  Sang Loong ,  Shyue Quek ,  Jun Song

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/76

    CPC分类号： H01L29/66772 ,  H01L29/78615

    摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

    摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

    Home gateway policy controlling device, system and implementing method thereof
    3.
    发明授权
    Home gateway policy controlling device, system and implementing method thereof 有权
    家庭网关策略控制设备，系统及其实现方法

    公开(公告)号：US08788646B2

    公开(公告)日：2014-07-22

    申请号：US13054181

    申请日：2008-12-18

    申请人： Jun Song ,  Mo Sun

    发明人： Jun Song ,  Mo Sun

    IPC分类号： G06F15/173 ,  H04L12/28 ,  H04L12/56 ,  H04L12/24

    CPC分类号： H04L12/2834 ,  H04L41/5003 ,  H04L47/10

    摘要： An apparatus for implementing policy control for home gateway comprises a Co-located Policy Decision Function Entity (PD-FE) for receiving the QoS policy issued by the PD-FE at network side and sending the QoS policy to the home gateway or issuing the QoS policy configured thereon to the home gateway. A method for implementing the policy control for home gateway, the method comprises: the Co-located PD-FE receiving the QoS policy issued by the PD-FE at network side or being configured with the QoS policy; and the Co-located PD-FE issuing the QoS policy to home gateways. With the present invention, the Resource and Admission Control Function (RACF) avoids controlling the home gateway directly or sending the policy to the home gateways in the case that there are a lot of home gateways and all the home gateways are scattered at the edge of the network.

    摘要翻译： 用于实现家庭网关策略控制的装置包括一个共同定位的策略决策功能实体（PD-FE），用于接收由网络侧的PD-FE发出的QoS策略，并将QoS策略发送到家庭网关或发出QoS 策略配置在家庭网关上。 一种实现家庭网关策略控制的方法，该方法包括：同时配置PD-FE接收由网络侧PD-FE发布的QoS策略，或配置QoS策略; 以及向家庭网关发布QoS策略的共同配置的PD-FE。 在本发明中，资源和接纳控制功能（RACF）避免了直接控制家庭网关或者在家庭网关有很多家庭网关的情况下向家庭网关发送策略，并且所有家庭网关都在 网络。

    Method for resource and admission control
    4.
    发明授权
    Method for resource and admission control 有权
    资源和准入控制方法

    公开(公告)号：US08472317B2

    公开(公告)日：2013-06-25

    申请号：US12999345

    申请日：2009-10-20

    申请人： Jianjie You ,  Mo Sun ,  Jun Song

    发明人： Jianjie You ,  Mo Sun ,  Jun Song

    IPC分类号： H04L1/00 ,  H04L12/26

    CPC分类号： H04W12/08 ,  H04L65/1043 ,  H04L65/80 ,  H04W28/24

    摘要： The present invention provides a method for resource and admission control. In the process of resource requesting: upon receiving a resource initialization request, which is used for requesting a QoS resource for a service, sent by an SCF, a PD-FE of a visited network performing an authorization check and a resource availability check for the resource initialization request, and sending the resource initialization request to a PD-FE of a home network; the PD-FE of the home network performing an authorization check and making an initial policy decision for the resource initialization request, and sending a resource initialization response containing the generated initial policy decision to the PD-FE of the visited network; and the PD-FE of the visited network making a final admission decision for the resource initialization request according to the initial decision policy and the result of the resource availability check. The method provided by the present invention specifies respective functional attributes of the PACF in the home network and of the PACF in the visited network and the interaction process between the two, and solves the problem of resource and admission control supporting roaming.

    摘要翻译： 本发明提供了一种用于资源和准入控制的方法。 在资源请求的过程中：在接收到由SCF发送的用于请求服务的QoS资源的资源初始化请求时，访问网络的PD-FE执行授权检查和资源可用性检查 资源初始化请求，并将资源初始化请求发送到家庭网络的PD-FE; 家庭网络的PD-FE执行授权检查并对资源初始化请求进行初始策略决定，并将包含所生成的初始策略决定的资源初始化响应发送到被访问网络的PD-FE; 访问网络的PD-FE根据初始决策策略和资源可用性检查的结果对资源初始化请求进行最终准入决定。 本发明提供的方法在归属网络和受访网络中的PACF以及两者之间的交互过程中规定了PACF的功能属性，解决了支持漫游的资源和准入控制问题。

    METHOD AND SYSTEM FOR CONTROLLING HOME GATEWAY POLICY
    5.
    发明申请
    METHOD AND SYSTEM FOR CONTROLLING HOME GATEWAY POLICY 审中-公开
    控制家庭网关策略的方法与系统

    公开(公告)号：US20100309926A1

    公开(公告)日：2010-12-09

    申请号：US12864223

    申请日：2008-05-23

    申请人： Mo Sun ,  Jun Song

    发明人： Mo Sun ,  Jun Song

    IPC分类号： H04L12/56

    CPC分类号： H04L41/0893 ,  H04L12/4641 ,  H04L12/66 ,  H04L41/5003 ,  H04L45/24 ,  H04L47/20 ,  H04L47/24 ,  H04L47/70 ,  H04L47/782 ,  H04L47/805 ,  H04W28/08 ,  H04W72/00 ,  H04W88/16

    摘要： A method and system for controlling home gateway policy are disclosed. The method comprises: a Resource and Admission Control Function (RACF) entity sends down a policy to a home gateway, and the home gateway performs a policy execution for an uplink packet passing through the home gateway according to the policy received. With the policy control method and system of the present invention, the policy is sent down to the home gateway through the RACF, Quality of Service (QoS) control is made for the uplink packet passing through the home gateway before Bandwidth Remote Access Server (BRAS), effective QoS assurance is provided for the uplink packets before arriving at the BRAS, and meanwhile, the problem of heavy load of a convergence layer of a metropolitan area network in the prior art is solved.

    摘要翻译： 公开了一种用于控制家庭网关策略的方法和系统。 该方法包括：资源和接纳控制功能（RACF）实体向家庭网关发送策略，家庭网关根据收到的策略对通过家庭网关的上行链路分组进行策略执行。 利用本发明的策略控制方法和系统，该策略通过RACF向家庭网关发送，对带宽远程访问服务器（BRAS）之前通过家庭网关的上行数据包进行服务质量（QoS）控制 ），在到达BRAS之前为上行链路分组提供了有效的QoS保证，同时解决了现有技术中城域网融合层重负载问题。

    ESD protection structure
    7.
    发明授权
    ESD protection structure 失效
    ESD保护结构

    公开(公告)号：US06835985B2

    公开(公告)日：2004-12-28

    申请号：US09733836

    申请日：2000-12-09

    申请人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

    发明人： Jun Cai ,  Guang Ping Hua ,  Jun Song ,  Keng Foo Lo

    IPC分类号： H01L2362

    CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A transistor structure is provided for ESD protection in an integrated circuit device. A semiconductor substrate has source and drain diffusion regions and respective source and drain wells under the source and drain diffusion regions. A shallow trench isolation formed over the semiconductor substrate and into the semiconductor substrate separates the source and drain diffusion regions and a portion of the source and drain wells. Source and drain contact structures respectively formed on the shallow trench isolation over the source and drain diffusion regions and extend through the shallow trench isolation to contact the source and drain diffusion regions. An ion implantation is performed through the contact openings into the bottoms of the source and drain wells to control the device trigger voltage and position the discharge current far away from the surface, which increases the device ESD performance significantly.

    Method of body contact for SOI mosfet
    8.
    发明授权
    Method of body contact for SOI mosfet 有权
    SOI mosfet的身体接触方法

    公开(公告)号：US06787422B2

    公开(公告)日：2004-09-07

    申请号：US09755572

    申请日：2001-01-08

    申请人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

    发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L29/78615

    摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

    摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

    Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers
    9.
    发明授权
    Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers 有权
    用于形成具有位于L形间隔物下方的源极/漏极延伸区域的MOSFET器件的方法

    公开(公告)号：US06455384B2

    公开(公告)日：2002-09-24

    申请号：US09972645

    申请日：2001-10-09

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

    摘要翻译： 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。