公开(公告)号：US20070190769A1

公开(公告)日：2007-08-16

申请号：US11418501

申请日：2006-05-03

申请人： Ting Ang

发明人： Ting Ang

IPC分类号： H01L21/44

CPC分类号： H01L21/02131 ,  C23C16/30 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31604 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/7684 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

摘要翻译： 提供一种形成半导体器件的方法。 在一个实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括沉积覆盖表面区域的介电层。 介电层通过CVD工艺形成。 此外，该方法包括形成覆盖在电介质层上的扩散阻挡层。 此外，该方法包括形成覆盖扩散阻挡层的导电层。 另外，该方法包括使用化学机械抛光工艺来减小导电层的厚度。 CVD工艺利用氟作为反应物形成电介质层。 此外，介电层与等于或小于3.3的介电常数相关联。

公开(公告)号：US20070161203A1

公开(公告)日：2007-07-12

申请号：US11321408

申请日：2005-12-28

申请人： Ting Ang

发明人： Ting Ang

IPC分类号： H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612

摘要： A method for filling a trench includes forming a first layer in a trench in order to partially fill the trench, removing at least a potion of the first layer from the trench; and forming a second layer on the first layer, wherein the forming a second layer is performed at a temperature of at least 700 degrees C. and at a gas flow ratio of at least 1.6, the gas flow ratio being equal to a first gas flow rate for a first gas to a second gas flow rate for a second gas. In a specific embodiment, the method includes removing a contaminant from the first layer by reacting with the contaminant present in the first layer at the temperature and with the gas flow ratio. In a specific embodiment, the removing at least a portion of the first layer includes etching the portion of the first layer.

摘要翻译： 用于填充沟槽的方法包括在沟槽中形成第一层以便部分地填充沟槽，从沟槽去除至少一部分第一层; 以及在所述第一层上形成第二层，其中所述形成第二层在至少700℃的温度和至少为1.6的气体流量比下进行，所述气体流量比等于第一气流 速率为第一气体到第二气体的第二气体流速。 在一个具体实施方案中，该方法包括通过在温度和气体流量比下与存在于第一层中的污染物反应从第一层去除污染物。 在具体实施例中，去除第一层的至少一部分包括蚀刻第一层的一部分。

公开(公告)号：US20070134900A1

公开(公告)日：2007-06-14

申请号：US11394529

申请日：2006-03-30

申请人： Ting Ang

发明人： Ting Ang

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/7685 ,  H01L21/76862

摘要： A method for manufacturing a semiconductor device is provided. In a specific embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. Additionally, the method includes forming a dielectric layer overlying the surface region and forming a diffusion barrier layer overlying the dielectric layer. Moreover, the method includes subjecting the diffusion barrier layer to a plasma environment to facilitate adhesion between the diffusion barrier layer and the dielectric layer at an interface region. Also, the method includes processing the semiconductor substrate while maintaining attachment between the dielectric layer and the diffusion barrier layer at the interface region. The subjecting the diffusion barrier layer to a plasma environment includes maintaining a thickness of the barrier diffusion layer.

摘要翻译： 提供一种制造半导体器件的方法。 在具体实施例中，该方法包括提供具有表面区域的半导体衬底。 表面区域包括覆盖半导体衬底的一个或多个层。 此外，该方法包括形成覆盖表面区域并形成覆盖在电介质层上的扩散阻挡层的电介质层。 此外，该方法包括使扩散阻挡层经受等离子体环境以促进在界面区域处的扩散阻挡层和电介质层之间的粘附。 此外，该方法包括处理半导体衬底，同时保持介电层和界面区域处的扩散阻挡层之间的附着。 将扩散阻挡层经受等离子体环境包括保持阻挡扩散层的厚度。

公开(公告)号：US20060110902A1

公开(公告)日：2006-05-25

申请号：US11249141

申请日：2005-10-11

申请人： Ting Ang

发明人： Ting Ang

IPC分类号： H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76871

摘要： A method for making an electrode in a semiconductor device. The method includes forming a trench in a first layer. The first layer is associated with a top surface, and the trench is associated with a bottom surface and a side surface. Additionally, the method includes depositing a diffusion barrier layer on at least the bottom surface, the side surface, and a part of the top surface, removing the diffusion barrier layer from at least a part of the bottom surface, depositing a seed layer on at least the part of the bottom surface and the diffusion barrier layer, and depositing an electrode layer on the seed layer.

摘要翻译： 一种在半导体器件中制造电极的方法。 该方法包括在第一层中形成沟槽。 第一层与顶表面相关联，并且沟槽与底表面和侧表面相关联。 此外，该方法包括在至少底表面，侧表面和顶表面的一部分上沉积扩散阻挡层，从底表面的至少一部分去除扩散阻挡层，将种子层沉积在 至少部分底表面和扩散阻挡层，以及在种子层上沉积电极层。

公开(公告)号：US20070128860A1

公开(公告)日：2007-06-07

申请号：US11320871

申请日：2005-12-28

申请人： Kuan Hou ,  Shou Lan ,  Rui Dong ,  Ting Ang

发明人： Kuan Hou ,  Shou Lan ,  Rui Dong ,  Ting Ang

IPC分类号： H01L21/44 ,  C23C16/00

CPC分类号： C23C16/4412 ,  H01L21/76834

摘要： A method and apparatus for depositing a dielectric layer. The apparatus includes a semiconductor processing chamber configured for use in a dielectric layer deposition process, the semiconductor processing chamber being associated with at least a length, a width, a height, and a volume, one or more gas sources containing one or more gases used in the barrier layer deposition process, and one or more gas flow controllers coupled to the one or more gas sources, the one or more gas flow controllers configured to provide one or more controlled amounts of one or more gas flows to the semiconductor processing chamber during semiconductor processing. One or more gas lines coupled to the one or more gas flow controllers for receiving one or more gas flows from the one or more gas flow controllers, and a pumping system is coupled to the semiconductor processing chamber, the pumping system configured to remove a quantity of gas from either the semiconductor processing chamber or the one or more gas lines. A 3-way valve is coupled to the pumping system and the process chamber, the 3-way valve being configured to allow the one or more gas flows to be sent to the pumping system or to the process chamber.

摘要翻译： 一种沉积介电层的方法和装置。 该设备包括被配置用于介电层沉积工艺中的半导体处理室，半导体处理室至少与长度，宽度，高度和体积相关联，一个或多个气体源包含一种或多种使用的气体 在所述阻挡层沉积工艺中，以及耦合到所述一个或多个气体源的一个或多个气体流量控制器，所述一个或多个气体流量控制器被配置为在半导体处理室期间向所述半导体处理室提供一个或多个受控量的一个或多个气体流 半导体加工。 耦合到所述一个或多个气体流量控制器的一个或多个气体管线用于接收来自所述一个或多个气体流量控制器的一个或多个气体流，以及泵送系统耦合到所述半导体处理室，所述泵送系统被配置为去除数量 来自半导体处理室或一个或多个气体管线的气体。 三通阀联接到泵送系统和处理室，三通阀被配置成允许一个或多个气流被送到泵送系统或处理室。

公开(公告)号：US20050014294A1

公开(公告)日：2005-01-20

申请号：US10915670

申请日：2004-08-10

申请人： Ting Ang ,  Sang Loong ,  Shyue Quek ,  Jun Song

发明人： Ting Ang ,  Sang Loong ,  Shyue Quek ,  Jun Song

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L21/76

CPC分类号： H01L29/66772 ,  H01L29/78615

摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。