公开(公告)号：US06372634B1

公开(公告)日：2002-04-16

申请号：US09333459

申请日：1999-06-15

Applicant: Jianmin Qiao ,  Sanjay Thekdi ,  Manuj Rathor ,  James E. Nulty

Inventor： Jianmin Qiao ,  Sanjay Thekdi ,  Manuj Rathor ,  James E. Nulty

IPC: H01L213065

CPC classification number: H01L21/31116 ,  H01L21/76802 ,  H01L21/76816

Abstract: A plasma etch chemistry and etch methodology is provided to improve critical dimension control for openings formed into and/or through a semiconductor thin film. According to an embodiment, the plasma etch chemistry includes an etchant mixture comprising a first etchant of the formula CxHyFz (where x≧2, y≧1 and z≧2) and a second etchant other than the first etchant to form the openings. The relationship of x, y and z may be such that y+z equals an even number ≦2x+2. According to an alternative embodiment, the plasma etch chemistry further includes strained cyclic (hydro)fluorocarbon. The plasma etch chemistry may be used to form openings in the layer in a single-etch step. In a further embodiment, the plasma etch chemistry described herein may etch less than the entire thickness of the layer, and a second plasma etch chemistry substantially free of the first etchant and strained cyclic (hydro)fluorocarbons etches the remainder of the layer to form the openings. Such an etch methodology advantageously reduces the risk of etching the materials underlying the layer.

Abstract translation: 提供等离子体蚀刻化学和蚀刻方法以改进形成于和/或穿过半导体薄膜的开口的临界尺寸控制。 根据实施例，等离子体蚀刻化学品包括蚀刻剂混合物，其包含式C x H y F z（其中x> = 2，y> = 1和z> = 2）的第一蚀刻剂和除第一蚀刻剂之外的第二蚀刻剂， 开口 x，y和z的关系可以使得y + z等于偶数<= 2x + 2。 根据替代实施例，等离子体蚀刻化学品还包括应变的环状（氢）氟碳化合物。 等离子体蚀刻化学可以用于在单蚀刻步骤中在层中形成开口。 在另一个实施方案中，本文所述的等离子体蚀刻化学蚀刻可以蚀刻小于层的整个厚度，并且基本上不含第一蚀刻剂的第二等离子体蚀刻化学品和应变的环状（氢）氟碳化物蚀刻该层的其余部分，形成 开口 这种蚀刻方法有利地降低了蚀刻层之下的材料的风险。

公开(公告)号：US06979652B2

公开(公告)日：2005-12-27

申请号：US10118763

申请日：2002-04-08

Applicant: Anisul Khan ,  Sharma V Pamarthy ,  Sanjay Thekdi ,  Ajay Kumar

Inventor： Anisul Khan ,  Sharma V Pamarthy ,  Sanjay Thekdi ,  Ajay Kumar

IPC: C23F1/00 ,  H01L21/302 ,  H01L21/3065

CPC classification number: H01L21/30655

Abstract: Openings of variable shape are made sequentially by alternately etching an opening in silicon and depositing a conformal fluorocarbon polymer on the sidewalls. This polymer protects the sidewalls of the opening from further etching. An isotropic etch can be carried out to change the profile of the etched feature, and for lift-off of the etched feature from the silicon substrate.

Abstract translation: 通过交替蚀刻硅中的开口并在侧壁上沉积共形氟碳聚合物来顺序地制备可变形状的开口。 该聚合物保护开口的侧壁进一步蚀刻。 可以进行各向同性蚀刻以改变蚀刻特征的轮廓，并且用于从硅衬底剥离蚀刻的特征。

公开(公告)号：US06979640B1

公开(公告)日：2005-12-27

申请号：US10112572

申请日：2002-03-29

Applicant: Alain Blosse ,  Sanjay Thekdi

Inventor： Alain Blosse ,  Sanjay Thekdi

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of making a semiconductor structure comprises forming a hole through a first dielectric layer; followed by forming a hole through an etch-stop layer, to expose a first conducting layer. The thickness of the etch-stop layer is at least one-half the smallest line width of the first conducting layer.

Abstract translation: 制造半导体结构的方法包括：通过第一介电层形成孔; 随后通过蚀刻停止层形成孔，以露出第一导电层。 蚀刻停止层的厚度是第一导电层的最小线宽的至少二分之一。

公开(公告)号：US20050031968A1

公开(公告)日：2005-02-10

申请号：US10736295

申请日：2003-12-15

Applicant: Barthelemy Fondeur ,  Anca Sala ,  Robert Brainard ,  David Nakamoto ,  Tom Truong ,  Sanjay Thekdi ,  Anantharaman Vaidyanathan

Inventor： Barthelemy Fondeur ,  Anca Sala ,  Robert Brainard ,  David Nakamoto ,  Tom Truong ,  Sanjay Thekdi ,  Anantharaman Vaidyanathan

IPC: G03C5/00 ,  G03F1/14 ,  G03F7/20 ,  G03F9/00

CPC classification number: G03F7/70466 ,  G03F1/50 ,  G03F1/70

Abstract: The present application relates to a method of fabricating planar circuits using a photolithographic mask set, to the photolithographic mask set, and to a planar circuit fabricated with the photolithographic mask set. The instant invention involves separating a photolithographic mask into two parts, namely, a master mask and one or more slave masks. The master mask and the one or more slave masks form a photolithographic mask set that is used iteratively to fabricate the planar circuits. In particular, the master mask is used as a template to provide the general layout for the planar circuit, while each slave mask is varied to tune and/or tailor the planar circuit. Since only a small portion of the planar circuit is redesigned and/or rewritten as a new mask (i.e., the slave mask), the instant invention provides a simple and cost effective method for optimizing planar circuits. Furthermore, since most mask errors will originate from the master mask, the instant invention provides an efficient method of correcting errors on planar circuits using the one or more slave masks.

Abstract translation: 本申请涉及使用光刻掩模组，光刻掩模组以及用光刻掩模组制造的平面电路来制造平面电路的方法。 本发明涉及将光刻掩模分为两部分，即主掩模和一个或多个从属掩模。 主掩模和一个或多个从属掩模形成用于迭代地制造平面电路的光刻掩模组。 特别地，主掩模用作模板以提供用于平面电路的总体布局，而每个从屏蔽被改变以调谐和/或定制平面电路。 由于只有一小部分平面电路被重新设计和/或重写为新的掩模（即，从属掩模），本发明提供了一种用于优化平面电路的简单且成本有效的方法。 此外，由于大多数掩模错误将源自主掩模，本发明提供了使用一个或多个从属掩码来校正平面电路上的误差的有效方法。

公开(公告)号：US20050135728A1

公开(公告)日：2005-06-23

申请号：US11015223

申请日：2004-12-17

Applicant: Anca Sala ,  Duncan Harwood ,  Barthelemy Fondeur ,  Anantharaman Vaidyanathan ,  Robert Brainard ,  Sanjay Thekdi ,  Thomas Nguyen ,  Ian Hutagalung

Inventor： Anca Sala ,  Duncan Harwood ,  Barthelemy Fondeur ,  Anantharaman Vaidyanathan ,  Robert Brainard ,  Sanjay Thekdi ,  Thomas Nguyen ,  Ian Hutagalung

IPC: G02B6/12 ,  G02B6/26 ,  G02F1/01 ,  G02F1/21

CPC classification number: G02F1/0147 ,  G02B6/12007 ,  G02B6/266 ,  G02F1/21 ,  G02F2001/0113 ,  G02F2001/212 ,  G02F2203/06

Abstract: The invention relates to a variable optical attenuator constructed as a Mach Zehnder planar lightwave circuit, particularly including a channel waveguide support structure for heat isolation and stress relief to reduce polarization dependent loss (PDL) and power consumption in the device. Power reduction trenches comprise longitudinal segments having small stress relief pillars of cladding material left in between them in the etching process. The waveguides of the MZI are supported by a main pillar structure and integral stress relief pillars which remain after removal of the trenches. The waveguide is surrounded by air on three sides for improved heat isolation. The performance of the present invention shows substantial improvement in PDL and extinction ratio over the prior art continuous trench design, and also, to a smaller degree, over the case where power reduction trenches are not used at all. Segmented trenches appear to allow for the lowest stress on the two waveguide arms of all the cases including no trench and trenched devices.

Abstract translation: 本发明涉及一种构成马赫曾德平面光波回路的可变光衰减器，特别是包括用于隔热和应力释放的通道波导支撑结构，以减少器件中的偏振相关损耗（PDL）和功耗。 功率减小沟槽包括在蚀刻工艺中在它们之间具有小的应力消除柱的包层材料的纵向段。 MZI的波导由主柱结构和消除沟槽后保留的积分应力消除柱支撑。 波导三面被空气包围，以改善热隔离。 与现有技术的连续沟槽设计相比，本发明的性能显示出PDL和消光比的显着改善，并且在更少的程度上，在完全不使用功率降低沟槽的情况下。 分段沟槽似乎允许在所有情况下的两个波导臂上的最小应力，包括没有沟槽和沟槽的器件。

公开(公告)号：US06696365B2

公开(公告)日：2004-02-24

申请号：US10041540

申请日：2002-01-07

Applicant: Ajay Kumar ,  Anisul Khan ,  Sanjay Thekdi ,  Dragan V. Podlesnik

Inventor： Ajay Kumar ,  Anisul Khan ,  Sanjay Thekdi ,  Dragan V. Podlesnik

IPC: H01L21302

CPC classification number: H01L21/3081 ,  H01L21/0276 ,  H01L21/3065 ,  H01L21/31116

Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

Abstract translation: 一种在涂覆有多层掩模的硅衬底中蚀刻高纵横比的各向异性深沟槽开口的方法，其中依次包括衬垫氧化物层，氮化硅层，掺杂或未掺杂的氧化硅硬掩模层，多晶硅硬掩模层， 抗反射涂层和图案化的光致抗蚀剂层，其包括使抗反射涂层和硬掩模层图案化，用氧去除光致抗蚀剂和抗反射层，使用图案化多晶硅作为蚀刻氧化硅硬掩模层中的开口的硬掩模层 ，氮化硅层和焊盘氧化物层，用CF4 / CHF3去除多晶硅硬掩模层，并使用图案化的氧化硅硬掩模层作为掩模蚀刻硅衬底中的各向异性深沟槽，以及包括三氟化氮的蚀刻剂混合物 自我清理的房间。

公开(公告)号：US06322716B1

公开(公告)日：2001-11-27

申请号：US09385187

申请日：1999-08-30

Applicant: Jianmin Qiao ,  Sanjay Thekdi

Inventor： Jianmin Qiao ,  Sanjay Thekdi

IPC: H01L21306

CPC classification number: H01J37/32862 ,  H01J37/321 ,  Y10S438/905

Abstract: A method for conditioning a plasma etch chamber is presented. A plasma etch chamber is provided, which preferably includes a chuck for supporting a topography. A conditioning process may be performed in the etch chamber. The conditioning process preferably includes positioning a cover topography on or above the chuck. A conditioning feed gas containing (hydro)halocarbons may be introduced into the chamber. A conditioning plasma may be generated from the conditioning feed gas for a conditioning time. Immediately after generating the conditioning plasma is complete, the overall thickness of the cover topography is preferably at least as great as immediately before generating the conditioning plasma. By performing a conditioning process in such a manner, the total cost and complexity of the conditioning process may be reduced.

Abstract translation: 提出了一种用于调节等离子体蚀刻室的方法。 提供了等离子体蚀刻室，其优选地包括用于支撑地形的卡盘。 可以在蚀刻室中进行调节处理。 调理过程优选地包括将盖子的形貌定位在卡盘上或上方。 含有（氢）卤代烃的调节进料气体可以引入该室。 可以从调理进料气体产生调理等离子体用于调理时间。 在产生调理等离子体之后立即完成，覆盖形貌的总体厚度优选至少等于产生调理等离子体之前的厚度。 通过以这种方式进行调节处理，可以降低调节处理的总成本和复杂性。