公开(公告)号：US20060271728A1

公开(公告)日：2006-11-30

申请号：US11420846

申请日：2006-05-30

申请人： Rosalino Critelli ,  Santi Adamo ,  Alessandro Inglese ,  Stefano Catalano ,  Edmondo Gangi

发明人： Rosalino Critelli ,  Santi Adamo ,  Alessandro Inglese ,  Stefano Catalano ,  Edmondo Gangi

IPC分类号： G06F12/00

CPC分类号： G06F9/4403 ,  G06F8/60

摘要： A low area architecture for embedded programming flash memory portions in microcontrollers is based on substitution of the ROM/RAM/CORE functionality with a digital ISP controller implemented in a finite state machine and a standard interface. After connecting ports of the embedded programming flash memory portion and releasing a RESET pin, the microcontroller enters a particular operating mode and is managed by the digital ISP controller instead of the CORE. The ROM is not required to set up the microcontroller, and as a consequence, transfer of the boot program from the ROM to the RAM is not requested for subsequent execution.

摘要翻译： 用于微控制器中嵌入式编程闪存部分的低面积架构是基于在有限状态机和标准接口中实现的数字ISP控制器代替ROM / RAM / CORE功能。 在连接嵌入式编程闪存部分的端口并释放RESET引脚后，微控制器进入特定的工作模式，由数字ISP控制器代替CORE进行管理。 ROM不需要设置微控制器，因此，引导程序从ROM传输到RAM不被要求后续执行。

公开(公告)号：US20070257710A1

公开(公告)日：2007-11-08

申请号：US11430527

申请日：2006-05-08

申请人： Ugo Mari ,  Santi Adamo ,  Gaetano Di Stefano ,  Fabrizio Meli

发明人： Ugo Mari ,  Santi Adamo ,  Gaetano Di Stefano ,  Fabrizio Meli

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： A circuit switches between at least a first clock signal and a second clock signal belonging to a plurality of clock signals available in an electronic device in response to the corresponding switch command, which comprises a selection module to select at a switch instant said second clock signal in said plurality of clock signals under the control of a signal selector and provide a selected clock signal. According to the invention said circuit comprises a logic-based filter module located downstream of said selection module and configured to produce an outgoing clock signal filtered under the control of a filter signal and also includes a control module configured to receive said switch command and to send said select signal to said selection module delaying said switch instant by a first interval of time, said control module also being configured to send said active filter signal for filtering to said filter module in a second interval of time that comprises an edge of the first clock signal and an edge of the second clock signal that are adjacent to said switching instant.

摘要翻译： A电路响应于相应的开关命令，在属于电子设备中可用的多个时钟信号的至少第一时钟信号和第二时钟信号之间切换，该选择模块包括选择模块，以在开关瞬间选择所述第二时钟信号 在所述多个时钟信号中，在信号选择器的控制下，提供所选择的时钟信号。 根据本发明，所述电路包括位于所述选择模块的下游的基于逻辑的滤波器模块，并且被配置为产生在滤波器信号的控制下被滤波的输出时钟信号，并且还包括控制模块，该控制模块被配置为接收所述开关命令并发送 所述选择模块对所述选择模块的所述选择信号延迟所述开关瞬间第一时间间隔，所述控制模块还被配置成在包括所述第一时钟的边沿的第二时间间隔内向所述滤波器模块发送所述有源滤波器信号以进行滤波 信号和与所述切换时刻相邻的第二时钟信号的边沿。

公开(公告)号：US20060236173A1

公开(公告)日：2006-10-19

申请号：US11301372

申请日：2005-12-12

申请人： Francesco Bombaci ,  Rosalino Critelli ,  Gianluca Aureliano ,  Santi Adamo

发明人： Francesco Bombaci ,  Rosalino Critelli ,  Gianluca Aureliano ,  Santi Adamo

IPC分类号： G01R31/28

CPC分类号： G06F11/167

摘要： A system for configuring registers of microcontrollers includes first register and second registers. The system includes a data source for loading a datum into the first register and the logic complement of said datum in the second register. The system also includes a comparator which verifies the identity between the datum in the first register and the logic complement in the second register, and, where the identity is not verified, generates a signal indicating that the data have been corrupted by a disturbance. The system also includes a final-state machine which disables the comparator during writing of the registers.

公开(公告)号：US20070022309A1

公开(公告)日：2007-01-25

申请号：US11482517

申请日：2006-07-06

申请人： Santi Adamo ,  Rosalino Critelli ,  Santi Pagano ,  Martino Quattrocchi

发明人： Santi Adamo ,  Rosalino Critelli ,  Santi Pagano ,  Martino Quattrocchi

IPC分类号： G06F1/00

CPC分类号： G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

摘要： A system for reducing power consumption in processing apparatus including a memory comprises a clock controller for controlling the clock period of the processing apparatus to switch the processing apparatus to a slow operating mode wherein the clock period is longer then the time required to recover from memory standby mode plus the time to execute a read command in the memory. A memory management module is provided configured for controlling the status of the memory during the slow operating mode by: maintaining the in a stand-by mode when no memory read/write commands are to be executed, and if any said read/write commands are required to be executed, switching said memory on only for the time required to perform the memory read/write commands.

摘要翻译： 一种用于在包括存储器的处理装置中降低功耗的系统包括时钟控制器，用于控制处理装置的时钟周期，以将处理装置切换到慢速操作模式，其中时钟周期长于从存储器备用恢复所需的时间 模式加上在内存中执行读取命令的时间。 提供了一种存储器管理模块，其被配置为在慢速操作模式期间通过以下操作来控制存储器的状态：当不执行存储器读/写命令时，保持处于备用模式，并且如果任何所述读/写命令是 需要执行，只有在执行存储器读/写命令所需的时间才切换所述存储器。