公开(公告)号：US08173507B2

公开(公告)日：2012-05-08

申请号：US12820214

申请日：2010-06-22

申请人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

发明人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

IPC分类号： H01L21/8247

CPC分类号： H01L21/823456 ,  H01L21/28114 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L27/11568 ,  H01L29/517

摘要： Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

摘要翻译： 方法包括在半导体材料上形成电荷存储晶体管栅叠层。 一个这样的堆叠包括隧道电介质，隧道电介质上的电荷存储材料，电荷存储材料上的高k电介质，以及高k电介质上的导电控制栅极材料。 该堆叠至少蚀刻到隧道电介质以在半导体材料上形成多个电荷存储晶体管栅极线。 栅极线的单独具有横向突出的脚，其包括高k电介质。 在蚀刻堆叠以形成栅极线之后，将离子注入到包括横向突出的脚的高k电介质的植入区域中。 离子对高k电介质是化学惰性的。 选择性地相对于植入区域外的高k电介质的部分蚀刻投影脚的离子注入的高k电介质。

公开(公告)号：US20110312171A1

公开(公告)日：2011-12-22

申请号：US12820214

申请日：2010-06-22

申请人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

发明人： Chan Lim ,  Jennifer Lequn Liu ,  Brian Dolan ,  Saurabh Keshav ,  Hongbin Zhu

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823456 ,  H01L21/28114 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L27/11568 ,  H01L29/517

摘要： Methods include forming a charge storage transistor gate stack over semiconductive material. One such stack includes a tunnel dielectric, charge storage material over the tunnel dielectric, a high-k dielectric over the charge storage material, and conductive control gate material over the high-k dielectric. The stack is etched at least to the tunnel dielectric to form a plurality of charge storage transistor gate lines over the semiconductive material. Individual of the gate lines have laterally projecting feet which include the high-k dielectric. After etching the stack to form the gate lines, ions are implanted into an implant region which includes the high-k dielectric of the laterally projecting feet. The ions are chemically inert to the high-k dielectric. The ion implanted high-k dielectric of the projecting feet is etched selectively relative to portions of the high-k dielectric outside of the implant region.

摘要翻译： 方法包括在半导体材料上形成电荷存储晶体管栅叠层。 一个这样的堆叠包括隧道电介质，隧道电介质上的电荷存储材料，电荷存储材料上的高k电介质，以及高k电介质上的导电控制栅极材料。 该堆叠至少蚀刻到隧道电介质以在半导体材料上形成多个电荷存储晶体管栅极线。 栅极线的单独具有横向突出的脚，其包括高k电介质。 在蚀刻堆叠以形成栅极线之后，将离子注入到包括横向突出的脚的高k电介质的植入区域中。 离子对高k电介质是化学惰性的。 选择性地相对于植入区域外的高k电介质的部分蚀刻投影脚的离子注入的高k电介质。