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公开(公告)号：US4979142A
公开(公告)日：1990-12-18
申请号：US339261
申请日：1989-04-17
CPC分类号： G06F7/535 , G06F2207/5352 , G06F7/4873
摘要： Apparatus and method for performing floating point divide operations in 2-bit, non-restoring iterations, wherein multiples of the divisor are formed by selective gating of one or more representations of the divisor into a single 3-input adder circuit, to calculate the partial quotients and subsequent partial dividends. The apparatus produces, without the need of separate holding registers, the zero, 1/2, 3/4, 1 and 3/2 multiples of the divisor.
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公开(公告)号：US4996660A
公开(公告)日：1991-02-26
申请号：US339268
申请日：1989-04-17
CPC分类号： G06F7/535 , G06F2207/5352 , G06F7/4873 , G06F7/49947 , G06F7/49957
摘要： A multiple selector logic circuit for selecting divisor multiples in 2-bit, non-restoring divide sequences, which provides a proper and accurate quotient result and remainder, and which produces rounding and indication of exact or inexact result in conformance with ANSI/IEEE Standard 754-1985; the multiple selector logic circuit incorporates semiconductor circuits including a multiplier table having a particular matrix of multipliers which meet the standard.
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公开(公告)号：US4941120A
公开(公告)日：1990-07-10
申请号：US339347
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49947
摘要： Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.
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4.发明授权
公开(公告)号：US4926370A
公开(公告)日：1990-05-15
申请号：US339348
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49957
摘要： A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.
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5.发明授权Floating-point processor having pre-adjusted exponent bias for multiplication and division 失效浮点处理器具有用于乘法和除法的预调整指数偏差
公开(公告)号：US4975868A
公开(公告)日：1990-12-04
申请号：US339279
申请日：1989-04-17
申请人： Donald L. Freerksen
发明人： Donald L. Freerksen
CPC分类号： G06F7/4876 , G06F7/535 , G06F7/5375 , G06F7/4873 , G06F7/4991 , G06F7/49936 , G06F7/49947
摘要： A floating-point arithmetic unit includes an exponent unit for biased exponents. Combinatorial bias-adjust logic removes the bias from one operand exponent before the two operand exponents are added together in adder for a multiply operation, and inserts a bias into one exponent before the exponents are subtracted by the adder for a divide operation.
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