公开(公告)号：US07034329B2

公开(公告)日：2006-04-25

申请号：US10992186

申请日：2004-11-18

申请人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

发明人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

IPC分类号： H01L29/06

CPC分类号： H01L29/152 ,  B82Y10/00 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7833

摘要： A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

摘要翻译： 半导体器件包括超晶格，其又包括多个堆叠的层组。 该装置还可以包括用于使载流子相对于堆叠的层组在平行方向上通过超晶格的运送的区域。 每个超晶格组可以包括限定基极半导体部分和其上的能带修饰层的多个层叠的基底半导体单层。 此外，能带修改层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。 因此，超晶格可以在平行方向上具有比否则将存在的更高的载流子迁移率。

公开(公告)号：US07659539B2

公开(公告)日：2010-02-09

申请号：US11381787

申请日：2006-05-05

申请人： Scott A. Kreps ,  Kalipatnam Vivek Rao

发明人： Scott A. Kreps ,  Kalipatnam Vivek Rao

IPC分类号： H01L29/06

CPC分类号： H01L21/28273 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.

摘要翻译： 半导体器件可以包括半导体衬底和至少一个非易失性存储单元。 所述至少一个存储单元可以包括间隔开的源极和漏极区域，以及在所述源极区域和漏极区域之间的所述半导体衬底上包括多个堆叠层组的超晶格沟道。 超晶格通道的每组层可以包括限定基底半导体部分和其上的能带修饰层的多个堆叠的基底半导体单层，其可以包括约束在相邻的基极半导体的晶格内的至少一个非半导体单层 部分。 浮置栅极可以与超晶格沟道相邻，并且控制栅极可以与第二栅极绝缘层相邻。

公开(公告)号：US07612366B2

公开(公告)日：2009-11-03

申请号：US11457256

申请日：2006-07-13

申请人： Robert J. Mears ,  Scott A. Kreps

发明人： Robert J. Mears ,  Scott A. Kreps

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/072

CPC分类号： H01L29/155 ,  H01L29/1054 ,  H01L29/152 ,  H01L29/7849

摘要： A semiconductor device may include a stress layer and a strained superlattice layer above the stress layer and including a plurality of stacked groups of layers. More particularly, each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

摘要翻译： 半导体器件可以包括应力层和应力层上方的应变超晶格层，并且包括多个堆叠的层组。 更具体地，应变超晶格层的每组层可以包括限定基极半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基极半导体部分的晶格内的至少一个非半导体单层。

公开(公告)号：US07598515B2

公开(公告)日：2009-10-06

申请号：US11457286

申请日：2006-07-13

申请人： Robert J. Mears ,  Scott A. Kreps

发明人： Robert J. Mears ,  Scott A. Kreps

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/072

CPC分类号： H01L29/152 ,  H01L29/1054 ,  H01L29/78 ,  H01L29/7849

摘要： A semiconductor device may include a strained superlattice layer including a plurality of stacked groups of layers, and a stress layer above the strained superlattice layer. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

摘要翻译： 半导体器件可以包括包含多个层叠层的应变超晶格层，以及在应变超晶格层之上的应力层。 应变超晶格层的每组层可以包括限定基极半导体部分的多个层叠的基底半导体单层以及约束在相邻的基极半导体部分的晶格内的至少一个非半导体单层。

公开(公告)号：US07265002B2

公开(公告)日：2007-09-04

申请号：US11042272

申请日：2005-01-25

申请人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

发明人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/155 ,  H01L29/7833

摘要： A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.

摘要翻译： 制造半导体器件的方法可以包括提供衬底，以及通过在最上层组上形成包括多层堆叠层和半导体帽层的超晶格，形成与衬底相邻的至少一个MOSFET。 超晶格的每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。 该方法还可以包括形成通过半导体盖层的至少一部分限定沟道的源极，漏极和栅极区域。

公开(公告)号：US06958486B2

公开(公告)日：2005-10-25

申请号：US10647060

申请日：2003-08-22

申请人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

发明人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

IPC分类号： H01L21/8238 ,  H01L29/10 ,  H01L29/15 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/152 ,  B82Y10/00 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/7833

摘要： A semiconductor device includes a superlattice that, in turn, includes a plurality of stacked groups of layers. The device may also include regions for causing transport of charge carriers through the superlattice in a parallel direction relative to the stacked groups of layers. Each group of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. Moreover, the energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Accordingly, the superlattice may have a higher charge carrier mobility in the parallel direction than would otherwise be present.

公开(公告)号：US07436026B2

公开(公告)日：2008-10-14

申请号：US10940426

申请日：2004-09-14

申请人： Scott A. Kreps

发明人： Scott A. Kreps

IPC分类号： H01L29/76

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/155 ,  H01L29/7833

摘要： A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The at least one MOSFET may include spaced apart source and drain regions in the semiconductor substrate, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice channel may have upper surface portions vertically stepped above adjacent upper surface portions of the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The at least one MOSFET may additionally include a gate overlying the superlattice channel.

摘要翻译： 半导体器件可以包括半导体衬底和至少一个金属氧化物半导体场效应晶体管（MOSFET）。 至少一个MOSFET可以包括在半导体衬底中的间隔开的源极和漏极区域，以及超晶格沟道，其在源极和漏极区域之间在半导体衬底上包括多个层叠的层组。 超晶格通道可以具有在源极和漏极区域的相邻上表面部分之上垂直阶梯的上表面部分。 超晶格通道的每组层可以包括在其上限定基极半导体部分和能带修饰层的多个层叠的基底半导体单层。 能带改性层可以包括约束在相邻基极半导体的晶格内的至少一个非半导体单层。 至少一个MOSFET可以另外包括覆盖超晶格通道的栅极。

公开(公告)号：US07435988B2

公开(公告)日：2008-10-14

申请号：US11042270

申请日：2005-01-25

申请人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

发明人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

IPC分类号： H01L29/06

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/155 ,  H01L29/7833

摘要： A semiconductor device may include a substrate and at least one MOSFET adjacent the substrate including a superlattice. The superlattice may include a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may comprise a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The MOSFET may further include source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.

摘要翻译： 半导体器件可以包括衬底和与包括超晶格的衬底相邻的至少一个MOSFET。 超晶格可以包括多个堆叠的层组，并且在最上层组上可以包括半导体盖层。 超晶格的每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。 MOSFET还可以包括通过半导体盖层的至少一部分限定沟道的源极，漏极和栅极区域。

公开(公告)号：US07303948B2

公开(公告)日：2007-12-04

申请号：US11089950

申请日：2005-03-25

申请人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

发明人： Robert J. Mears ,  Jean Augustin Chan Sow Fook Yiptong ,  Marek Hytha ,  Scott A. Kreps ,  Ilija Dukovski

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/155 ,  H01L29/7833

摘要： A semiconductor device includes a substrate, and at least one MOSFET adjacent the substrate. The MOSFET may include a superlattice channel that, in turn, includes a plurality of stacked groups of layers. The MOSFET may also include source and drain regions laterally adjacent the superlattice channel, and a gate overlying the superlattice channel for causing transport of charge carriers through the superlattice channel in a parallel direction relative to the stacked groups of layers. Each group of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions so that the superlattice channel may have a higher charge carrier mobility in the parallel direction than would otherwise occur.

摘要翻译： 半导体器件包括衬底和与衬底相邻的至少一个MOSFET。 MOSFET可以包括超晶格通道，其又包括多个堆叠的层组。 MOSFET还可以包括横向邻近超晶格沟道的源极和漏极区域，以及覆盖超晶格沟道的栅极，用于使电荷载流子相对于堆叠的层组在平行方向上通过超晶格沟道传输。 每组超晶格通道可以包括限定基极半导体部分的多个层叠的基底半导体单层，以及其上的能带修饰层。 能带修改层可以包括约束在相邻基底半导体部分的晶格内的至少一个非半导体单层，使得超晶格通道可以在平行方向上具有比否则发生的更高的载流子迁移率。

公开(公告)号：US07279701B2

公开(公告)日：2007-10-09

申请号：US10941062

申请日：2004-09-14

申请人： Scott A. Kreps

发明人： Scott A. Kreps

IPC分类号： H01L29/06

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L29/155 ,  H01L29/7833

摘要： A semiconductor device may include a semiconductor substrate and at least one metal oxide semiconductor field-effect transistor (MOSFET). The MOSFET may include spaced apart source and drain regions on the semiconductor substrate, and a superlattice including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. The superlattice may have upper portions extending above adjacent upper portions of the source and drain regions, and lower portions contacting the source and drain regions so that a channel is defined in lower portions of said superlattice. Furthermore, each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. A gate may overly the superlattice.

摘要翻译： 半导体器件可以包括半导体衬底和至少一个金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET可以在半导体衬底上包括间隔开的源极和漏极区域，以及在源极和漏极区域之间的半导体衬底上包括多个层叠的层的超晶格。 超晶格可以具有在源极和漏极区域的相邻上部之上延伸的上部，以及接触源极和漏极区域的下部，使得沟道限定在所述超晶格的下部。 此外，超晶格的每组层可以包括在其上限定基极半导体部分和能带改性层的多个层叠的基底半导体单层。 能带修改层可以包括约束在相邻基极半导体的晶格内的至少一个非半导体单层。 一个门可能会超过超晶格。