公开(公告)号：US07812339B2

公开(公告)日：2010-10-12

申请号：US12102305

申请日：2008-04-14

申请人： Robert J. Mears ,  Kalipatnam Vivek Rao

发明人： Robert J. Mears ,  Kalipatnam Vivek Rao

IPC分类号： H01L29/06

CPC分类号： H01L29/1054 ,  H01L21/76237 ,  H01L29/1033 ,  H01L29/15

摘要： A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer. The semiconductor device may further include a lateral spacer between the superlattice layer and the STI region and which may include a lower non-monocrystalline semiconductor superlattice portion and an upper dielectric portion.

摘要翻译： 半导体器件可以包括在半导体衬底中具有表面，浅沟槽隔离（STI）区域并在其表面之上延伸的半导体衬底和邻近半导体衬底的表面的超晶格层，并且包括多个层叠的 层。 更具体地，超晶格层的每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。 此外，来自相对的基底半导体部分的至少一些原子可以与穿过至少一个介入的非半导体单层的化学键化学地结合在一起。 半导体器件还可以包括在超晶格层和STI区之间的横向间隔物，并且其可以包括下部非单晶半导体超晶格部分和上部电介质部分。

公开(公告)号：US20080179664A1

公开(公告)日：2008-07-31

申请号：US12018260

申请日：2008-01-23

申请人： Kalipatnam Vivek Rao

发明人： Kalipatnam Vivek Rao

IPC分类号： H01L29/417 ,  H01L21/336

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0688 ,  H01L29/1054 ,  H01L29/158 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

摘要： A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

摘要翻译： 半导体器件可以在衬底上包括至少一个垂直金属氧化物半导体场效应晶体管（MOSFET）。 垂直MOSFET可以包括至少一个超晶格，其包括横跨于衬底的多个横向层叠的层组。 垂直MOSFET还可以包括横向邻近超晶格的栅极，以及垂直于超晶格上方和下方的区域，并与栅极配合，以使载流子在垂直方向上传输超晶格。 超晶格的每组层可以包括限定基极半导体部分的堆叠的基底半导体单层和约束在相邻的基极半导体部分的晶格内的至少一个非半导体单层。 来自相对的基底半导体部分的至少一些原子可以与穿过至少一个介入的非半导体单层的化学键化学地结合在一起。

公开(公告)号：US20080179588A1

公开(公告)日：2008-07-31

申请号：US12018255

申请日：2008-01-23

申请人： Kalipatnam Vivek Rao

发明人： Kalipatnam Vivek Rao

IPC分类号： H01L29/15 ,  H01L21/338

CPC分类号： H01L29/154 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66643

摘要： A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

摘要翻译： 可以包括半导体层的半导体器件和它们之间的超晶格界面层。 超晶格界面层可以包括多个堆叠的层组。 每组层可以包括限定基底半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。 来自相对的基底半导体部分的至少一些原子可以与穿过至少一个介入的非半导体单层的化学键化学地结合在一起。

公开(公告)号：US07928425B2

公开(公告)日：2011-04-19

申请号：US12018255

申请日：2008-01-23

申请人： Kalipatnam Vivek Rao

发明人： Kalipatnam Vivek Rao

IPC分类号： H01L29/06

CPC分类号： H01L29/154 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66643

摘要： A semiconductor device which may include a semiconductor layer, and a superlattice interface layer therebetween. The superlattice interface layer may include a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

摘要翻译： 可以包括半导体层的半导体器件和它们之间的超晶格界面层。 超晶格界面层可以包括多个堆叠的层组。 每组层可以包括限定基底半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。 来自相对的基底半导体部分的至少一些原子可以与穿过至少一个介入的非半导体单层的化学键化学地结合在一起。

公开(公告)号：US07586116B2

公开(公告)日：2009-09-08

申请号：US11381835

申请日：2006-05-05

申请人： Scott A. Kreps ,  Kalipatnam Vivek Rao

发明人： Scott A. Kreps ,  Kalipatnam Vivek Rao

IPC分类号： H04L29/06

CPC分类号： H01L21/28273 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78696 ,  H01L29/7881

摘要： A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

摘要翻译： 半导体器件可以包括衬底，与衬底相邻的绝缘层，以及邻近与衬底相对的绝缘层的表面的半导体层。 器件还可以包括半导体层上的源极和漏极区域，邻近半导体层并且在源极和漏极区域之间延伸以限定沟道的超晶格和覆盖超晶格的栅极。 超晶格可以包括多个堆叠的层组，其中每组层包括限定基底半导体部分和其上的能带修饰层的多个层叠的基底半导体单层。 能带修饰层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

公开(公告)号：US07446002B2

公开(公告)日：2008-11-04

申请号：US11136747

申请日：2005-05-25

申请人： Robert J. Mears ,  Marek Hytha ,  Scott A. Kreps ,  Robert John Stephenson ,  Jean Augustin Chan Sow Fook Yiptong ,  Ilija Dukovski ,  Kalipatnam Vivek Rao ,  Samed Halilov ,  Xiangyang Huang

发明人： Robert J. Mears ,  Marek Hytha ,  Scott A. Kreps ,  Robert John Stephenson ,  Jean Augustin Chan Sow Fook Yiptong ,  Ilija Dukovski ,  Kalipatnam Vivek Rao ,  Samed Halilov ,  Xiangyang Huang

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/152 ,  H01L29/155 ,  H01L29/513 ,  H01L29/7833

摘要： A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.

摘要翻译： 制造半导体器件的方法可以包括形成包含与衬底相邻的多个堆叠层组的超晶格。 超晶格的每组层可以包括限定基极半导体部分的多个层叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。 该方法还可以包括在电极层上形成高K电介质层，并在高K电介质层上形成与超晶格相对的电极层。

公开(公告)号：US07202494B2

公开(公告)日：2007-04-10

申请号：US11426969

申请日：2006-06-28

申请人： Richard A. Blanchard ,  Kalipatnam Vivek Rao ,  Scott A. Kreps

发明人： Richard A. Blanchard ,  Kalipatnam Vivek Rao ,  Scott A. Kreps

IPC分类号： H01L29/06

CPC分类号： H01L29/151 ,  B82Y10/00 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/7833

摘要： A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

摘要翻译： 半导体器件可以包括至少一个鳍状场效应晶体管（FINFET），其包括与鳍片的相对端相邻的翅片，源极和漏极区域以及覆盖鳍片的栅极。 翅片可以包括至少一个超晶格，其包括多个堆叠的层组。 每组层可以包括限定基底半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

公开(公告)号：US06297130B1

公开(公告)日：2001-10-02

申请号：US08113887

申请日：1993-08-30

申请人： Kalipatnam Vivek Rao

发明人： Kalipatnam Vivek Rao

IPC分类号： H01L21762

CPC分类号： H01L21/32

摘要： This is a method for forming a recessed LOCOS isolation region, which includes the steps of forming a first silicon nitride layer between the pad oxide layer and a polysilicon buffer layer and a second nitride layer over the polysilicon buffer layer. In addition, the method for forming LOCOS isolation regions can include the additional steps of forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation regions have provided a low-profile recessed field oxide with reduced oxide encroachment into the active moat region.

摘要翻译： 这是用于形成凹陷的LOCOS隔离区域的方法，其包括以下步骤：在多晶硅缓冲层之上在衬垫氧化物层和多晶硅缓冲层之间形成第一氮化硅层和第二氮化物层。 此外，用于形成LOCOS隔离区域的方法可以包括在场氧化步骤之前围绕活性壕沟区域的周边形成侧壁密封的附加步骤。 所得到的场氧化物隔离区域已经提供了一种具有减少的氧化物侵入到活性壕沟区域中的低轮廓凹陷场氧化物。

公开(公告)号：US07781827B2

公开(公告)日：2010-08-24

申请号：US12018260

申请日：2008-01-23

申请人： Kalipatnam Vivek Rao

发明人： Kalipatnam Vivek Rao

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/80

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/0688 ,  H01L29/1054 ,  H01L29/158 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

摘要： A semiconductor device may include at least one vertical Metal Oxide Semiconductor Field Effect Transistor (MOSFET) on a substrate. The vertical MOSFET may include at least one superlattice including a plurality of laterally stacked groups of layers transverse to the substrate. The vertical MOSFET(s) may further include a gate laterally adjacent the superlattice, and regions vertically above and below the superlattice and cooperating with the gate for causing transport of charge carriers through the superlattice in the vertical direction. Each group of layers of the superlattice may include stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. At least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

摘要翻译： 半导体器件可以在衬底上包括至少一个垂直金属氧化物半导体场效应晶体管（MOSFET）。 垂直MOSFET可以包括至少一个超晶格，其包括横跨于衬底的多个横向层叠的层组。 垂直MOSFET还可以包括横向邻近超晶格的栅极，以及垂直于超晶格上方和下方的区域，并与栅极配合，以使载流子在垂直方向上传输超晶格。 超晶格的每组层可以包括限定基极半导体部分的堆叠的基底半导体单层和约束在相邻的基极半导体部分的晶格内的至少一个非半导体单层。 来自相对的基底半导体部分的至少一些原子可以与穿过至少一个介入的非半导体单层的化学键化学地结合在一起。

公开(公告)号：US07659539B2

公开(公告)日：2010-02-09

申请号：US11381787

申请日：2006-05-05

申请人： Scott A. Kreps ,  Kalipatnam Vivek Rao

发明人： Scott A. Kreps ,  Kalipatnam Vivek Rao

IPC分类号： H01L29/06

CPC分类号： H01L21/28273 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.

摘要翻译： 半导体器件可以包括半导体衬底和至少一个非易失性存储单元。 所述至少一个存储单元可以包括间隔开的源极和漏极区域，以及在所述源极区域和漏极区域之间的所述半导体衬底上包括多个堆叠层组的超晶格沟道。 超晶格通道的每组层可以包括限定基底半导体部分和其上的能带修饰层的多个堆叠的基底半导体单层，其可以包括约束在相邻的基极半导体的晶格内的至少一个非半导体单层 部分。 浮置栅极可以与超晶格沟道相邻，并且控制栅极可以与第二栅极绝缘层相邻。