公开(公告)号：US07068078B2

公开(公告)日：2006-06-27

申请号：US10877556

申请日：2004-06-24

申请人： Seong-Jong Yoo

发明人： Seong-Jong Yoo

IPC分类号： H03K19/094

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

摘要： A data output driver, for use in a semiconductor memory device, includes a pull-up driving unit, having N numbers of unit pull-up drivers and N numbers of pull-up resistors, turned on by selected pull-up control signals for pull-up driving the output terminal in response to a pull-up data signal; and a pull-down driving unit, having N numbers of unit pull-down drivers and N numbers of pull-down resistors, turned on by selected pull-down control signals for pull-down driving the output terminal in response to a pull-down data signal, wherein each of the N numbers of unit pull-up drivers has the same driving strength, and the N numbers of pull-up resistors are connected between the output terminal and the N numbers of unit pull-up drivers; and each of the N numbers of unit pull-down drivers has the same driving strength, and the N numbers of pull-down resistors are connected between the output terminal and the N numbers of unit pull-down drivers.

摘要翻译： 用于半导体存储器件的数据输出驱动器包括具有N个单元上拉驱动器和N个上拉电阻的上拉驱动单元，通过所选择的上拉控制信号导通 响应于上拉数据信号驱动输出端; 以及具有N个单元下拉驱动器和N个下拉电阻器的下拉驱动单元，其通过选择的下拉控制信号导通，用于响应于下拉菜单来下拉驱动输出端子 数据信号，其中N个单元上拉驱动器中的每一个具有相同的驱动强度，并且N个上拉电阻连接在输出端子和N个单元上拉驱动器之间; 并且N个单元下拉驱动器中的每一个具有相同的驱动强度，并且N个下拉电阻器连接在输出端子和N个单元下拉驱动器之间。

公开(公告)号：US20050057281A1

公开(公告)日：2005-03-17

申请号：US10877556

申请日：2004-06-24

申请人： Seong-Jong Yoo

发明人： Seong-Jong Yoo

IPC分类号： G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  H03K19/003 ,  H03K19/0175

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C2207/105

摘要： A data output driver, for use in a semiconductor memory device, includes a pull-up driving unit, having N numbers of unit pull-up drivers and N numbers of pull-up resistors, turned on by selected pull-up control signals for pull-up driving the output terminal in response to a pull-up data signal; and a pull-down driving unit, having N numbers of unit pull-down drivers and N numbers of pull-down resistors, turned on by selected pull-down control signals for pull-down driving the output terminal in response to a pull-down data signal, wherein each of the N numbers of unit pull-up drivers has the same driving strength, and the N numbers of pull-up resistors are connected between the output terminal and the N numbers of unit pull-up drivers; and each of the N numbers of unit pull-down drivers has the same driving strength, and the N numbers of pull-down resistors are connected between the output terminal and the N numbers of unit pull-down drivers.

摘要翻译： 用于半导体存储器件的数据输出驱动器包括具有N个单元上拉驱动器和N个上拉电阻的上拉驱动单元，通过所选择的上拉控制信号导通 响应于上拉数据信号驱动输出端; 以及具有N个单元下拉驱动器和N个下拉电阻器的下拉驱动单元，其通过选择的下拉控制信号导通，用于响应于下拉菜单来下拉驱动输出端子 数据信号，其中N个单元上拉驱动器中的每一个具有相同的驱动强度，并且N个上拉电阻连接在输出端子和N个单元上拉驱动器之间; 并且N个单元下拉驱动器中的每一个具有相同的驱动强度，并且N个下拉电阻器连接在输出端子和N个单元下拉驱动器之间。

公开(公告)号：US20050057981A1

公开(公告)日：2005-03-17

申请号：US10882486

申请日：2004-06-30

申请人： Seong-Jong Yoo

发明人： Seong-Jong Yoo

IPC分类号： G11C7/10 ,  H03B1/00

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069 ,  G11C2207/2254

摘要： A semiconductor memory device comprises a data input/output pad; a data input unit for buffering and latching a data signal inputted through the data input/output pad during a data access operation, or for buffering and latching an OCD control code signal inputted through the data input/output pad during the OCD calibration control operation; a data align unit for aligning the data signal latched by the data input unit and transferring the aligned data signal to a memory core during the data access operation, or for aligning and outputting the OCD control code signal latched by the data input unit during the OCD calibration control operation; a data output driver for outputting and driving the data signal outputted from the memory core; and an OCD control unit for decoding the OCD control code signal outputted from the data align unit to thereby adjust an output impedance of the data output driver.

摘要翻译： 半导体存储器件包括数据输入/输出焊盘; 数据输入单元，用于在数据访问操作期间缓冲和锁存通过数据输入/输出焊盘输入的数据信号，或者用于缓冲和锁存在OCD校准控制操作期间通过数据输入/输出焊盘输入的OCD控制代码信号; 数据对准单元，用于对准由数据输入单元锁存的数据信号，并在数据存取操作期间将对准的数据信号传送到存储器核心，或者用于对准和输出由OCD中的数据输入单元锁存的OCD控制代码信号 校准控制操作; 数据输出驱动器，用于输出和驱动从存储器核心输出的数据信号; 以及OCD控制单元，用于对从数据对准单元输出的OCD控制代码信号进行解码，从而调整数据输出驱动器的输出阻抗。

公开(公告)号：US20140253534A1

公开(公告)日：2014-09-11

申请号：US14185445

申请日：2014-02-20

申请人： Jin-Han KIM ,  Jae-Wook KWON ,  Seong-Jong YOO ,  Ha-Jun LEE

发明人： Jin-Han KIM ,  Jae-Wook KWON ,  Seong-Jong YOO ,  Ha-Jun LEE

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291 ,  H03K5/04 ,  H03K19/00361

摘要： A source driving circuit includes an output buffer circuit to compensate for slew rate of signals used to drive a display device. The output buffer circuit includes a bias current control signal generating circuit and a channel amplifying circuit. The bias current control signal generating circuit performs an exclusive OR operation on an input signal and an output signal of a reference operational amplifier to generate a bias current control signal. The channel amplifying circuit adjusts the slew rate of a plurality of output voltage signals in response to the bias current control signal. The output signals are then used to control the display device.

摘要翻译： 源极驱动电路包括用于补偿用于驱动显示器件的信号的转换速率的输出缓冲器电路。 输出缓冲电路包括偏置电流控制信号发生电路和信道放大电路。 偏置电流控制信号发生电路对参考运算放大器的输入信号和输出信号执行异或运算，以产生偏置电流控制信号。 通道放大电路根据偏置电流控制信号调整多个输出电压信号的转换速率。 然后输出信号用于控制显示设备。

公开(公告)号：US07019556B2

公开(公告)日：2006-03-28

申请号：US10882486

申请日：2004-06-30

申请人： Seong-Jong Yoo

发明人： Seong-Jong Yoo

IPC分类号： H03K19/003

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1069 ,  G11C2207/2254

摘要： A semiconductor memory device comprises a data input/output pad; a data input unit for buffering and latching a data signal inputted through the data input/output pad during a data access operation, or for buffering and latching an OCD control code signal inputted through the data input/output pad during the OCD calibration control operation; a data align unit for aligning the data signal latched by the data input unit and transferring the aligned data signal to a memory core during the data access operation, or for aligning and outputting the OCD control code signal latched by the data input unit during the OCD calibration control operation; a data output driver for outputting and driving the data signal outputted from the memory core; and an OCD control unit for decoding the OCD control code signal outputted from the data align unit to thereby adjust an output impedance of the data output driver.

摘要翻译： 半导体存储器件包括数据输入/输出焊盘; 数据输入单元，用于在数据访问操作期间缓冲和锁存通过数据输入/输出焊盘输入的数据信号，或者用于缓冲和锁存在OCD校准控制操作期间通过数据输入/输出焊盘输入的OCD控制代码信号; 数据对准单元，用于对准由数据输入单元锁存的数据信号，并在数据存取操作期间将对准的数据信号传送到存储器核心，或者用于对准和输出由OCD中的数据输入单元锁存的OCD控制代码信号 校准控制操作; 数据输出驱动器，用于输出和驱动从存储器核心输出的数据信号; 以及OCD控制单元，用于对从数据对准单元输出的OCD控制代码信号进行解码，从而调整数据输出驱动器的输出阻抗。