公开(公告)号：US20160027795A1

公开(公告)日：2016-01-28

申请号：US14801470

申请日：2015-07-16

Applicant: WON-SEOK JUNG ,  Changseok KANG ,  SeungWoo PAEK ,  lnseok YANG ,  Kyungjoong JOO

Inventor： WON-SEOK JUNG ,  Changseok KANG ,  SeungWoo PAEK ,  lnseok YANG ,  Kyungjoong JOO

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device includes a substrate, a stack structure, peripheral gate structures and residual spacers. The substrate includes a cell array region and a peripheral circuit region. The stack structure is disposed on the cell array region, having electrodes and insulating layers alternately stacked. The peripheral gate structures are disposed on the peripheral circuit region, being spaced apart from each other in one direction and having a peripheral gate pattern disposed on the substrate, and a peripheral gate spacer disposed on a sidewall of the peripheral gate pattern. The residual spacers are disposed on sidewalls of the peripheral gate structures, having a sacrificial pattern and an insulating pattern that are stacked. The insulating pattern includes substantially the same material as the insulating layers of the stack structure.

Abstract translation: 半导体器件包括衬底，堆叠结构，外围栅极结构和残余间隔物。 衬底包括电池阵列区域和外围电路区域。 堆叠结构设置在电池阵列区域上，具有交替堆叠的电极和绝缘层。 外围栅极结构设置在外围电路区域上，在一个方向上彼此间隔开并且具有设置在基板上的周边栅极图案，以及设置在外围栅极图案的侧壁上的外围栅极间隔件。 剩余间隔物设置在外围栅极结构的侧壁上，具有堆叠的牺牲图案和绝缘图案。 绝缘图案包括与堆叠结构的绝缘层基本相同的材料。

公开(公告)号：US20150235939A1

公开(公告)日：2015-08-20

申请号：US14588506

申请日：2015-01-02

Applicant: Sunyeong LEE ,  Kyoung-Hoon KIM ,  Jin-Woo PARK ,  SeungWoo PAEK ,  Seok-won LEE ,  Taekeun CHO

Inventor： Sunyeong LEE ,  Kyoung-Hoon KIM ,  Jin-Woo PARK ,  SeungWoo PAEK ,  Seok-won LEE ,  Taekeun CHO

IPC: H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L2224/32145

Abstract: Three-dimensional (3D) semiconductor devices are provided. The 3D semiconductor device includes a plurality of dummy pillars penetrating each cell pad of an electrode structure and the electrode structure disposed under each cell pad. Insulating patterns of a mold stack structure for formation of the electrode structure may be supported by the plurality of dummy pillars, so transformation and contact of the insulating patterns may be minimized or prevented.

Abstract translation: 提供三维（3D）半导体器件。 3D半导体器件包括穿过电极结构的每个电池衬垫的多个虚拟柱和设置在每个电池衬垫下方的电极结构。 用于形成电极结构的模具堆叠结构的绝缘图案可以由多个虚拟支柱支撑，因此可以最小化或防止绝缘图案的变形和接触。