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    SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions
    1.
    发明授权
    SRAM cells having inverters and access transistors therein with vertical fin-shaped active regions 失效
    具有反相器和存取晶体管的SRAM单元具有垂直鳍状有源区

    公开(公告)号：US07368788B2

    公开(公告)日：2008-05-06

    申请号：US11375617

    申请日：2006-03-14

    申请人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    发明人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785

    摘要： Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

    摘要翻译： 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元包括形成为具有相反导电类型的堆叠半导体区域的鳍状图案的至少第一反相器。 在这些实施例的一些中，第一反相器包括与第二导电类型（例如，N型P型）MOS驱动器串联电耦合的第一导电类型（例如，P型或N型）MOS负载晶体管 晶体管。 第一反相器被布置成使得第一导电类型MOS负载晶体管和第二导电类型驱动晶体管的有源区在垂直双电导率半导体鳍结构的第一部分内相对于彼此垂直堆叠。 这种翅片结构在至少三面被环绕的栅电极包围，该环形栅电极被配置成响应于栅极信号调制两个有源区的电导率。

    CMOS SRAM cells employing multiple-gate transistors and methods fabricating the same
    2.
    发明申请
    CMOS SRAM cells employing multiple-gate transistors and methods fabricating the same 失效
    采用多栅极晶体管的CMOS SRAM单元及其制造方法

    公开(公告)号：US20060220134A1

    公开(公告)日：2006-10-05

    申请号：US11375617

    申请日：2006-03-14

    申请人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    发明人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    IPC分类号： H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785

    摘要： Complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells include at least a first inverter formed in a fin-shaped pattern of stacked semiconductor regions of opposite conductivity type. In some of these embodiments, the first inverter includes a first conductivity type (e.g., P-type or N-type) MOS load transistor electrically coupled in series with a second conductivity type (e.g., N-type of P-type) MOS driver transistor. The first inverter is arranged so that active regions of the first conductivity type MOS load transistor and the second conductivity type driver transistor are vertically stacked relative to each other within a first portion of a vertical dual-conductivity semiconductor fin structure. This fin structure is surrounded on at least three sides by a wraparound gate electrode, which is configured to modulate conductivity of both the active regions in response to a gate signal.

    摘要翻译： 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元包括形成为具有相反导电类型的堆叠半导体区域的鳍状图案的至少第一反相器。 在这些实施例的一些中，第一反相器包括与第二导电类型（例如，N型P型）MOS驱动器串联电耦合的第一导电类型（例如，P型或N型）MOS负载晶体管 晶体管。 第一反相器被布置成使得第一导电类型MOS负载晶体管和第二导电类型驱动晶体管的有源区在垂直双电导率半导体鳍结构的第一部分内相对于彼此垂直堆叠。 这种翅片结构在至少三面被环绕的栅电极包围，该环形栅电极被配置成响应于栅极信号调制两个有源区的电导率。

    Dram device and method of manufacturing the same
    5.
    发明申请
    Dram device and method of manufacturing the same 失效
    戏剧装置及其制造方法

    公开(公告)号：US20080246067A1

    公开(公告)日：2008-10-09

    申请号：US12149406

    申请日：2008-05-01

    申请人： Hong-Sik Yoon ,  In-Seok Yeo ,  Seung-Jae Baik ,  Zong-Liang Huo ,  Shi-Eun Kim

    发明人： Hong-Sik Yoon ,  In-Seok Yeo ,  Seung-Jae Baik ,  Zong-Liang Huo ,  Shi-Eun Kim

    IPC分类号： H01L29/78 ,  H01L21/8242

    CPC分类号： H01L27/10873 ,  H01L27/10829

    摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

    摘要翻译： 在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。 非导电图案具有比导电图案的带隙大的带隙。 在MTJ结构的侧壁上形成栅极绝缘层和栅电极。 字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。 电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因​​此DRAM器件需要较小的衬底表面积。

    Single transistor floating body DRAM cell having recess channel transistor structure and method of fabricating the same
    6.
    发明申请
    Single transistor floating body DRAM cell having recess channel transistor structure and method of fabricating the same 失效
    具有凹槽沟道晶体管结构的单晶体管浮体DRAM单元及其制造方法

    公开(公告)号：US20060220085A1

    公开(公告)日：2006-10-05

    申请号：US11335333

    申请日：2006-01-19

    申请人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    发明人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    IPC分类号： H01L29/94 ,  H01L21/8244

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841 ,  H01L29/78648

    摘要： Single transistor floating body dynamic random access memory (DRAM) cells include a semiconductor substrate and a barrier layer on the semiconductor substrate and a recess channel transistor on the barrier layer. The recess channel transistor includes a source region of a first conductivity type, a drain region of the first conductivity type spaced apart from the source region and a floating body of a second conductivity type between the barrier layer and the source region and the drain region. The floating body includes a recess region between the source region and the drain region. Methods of forming single transistor floating body dynamic random access memory (DRAM) cells are also provided.

    摘要翻译： 单晶体管浮体动态随机存取存储器（DRAM）单元包括半导体衬底和半导体衬底上的阻挡层以及阻挡层上的凹槽通道晶体管。 凹槽沟道晶体管包括第一导电类型的源极区域，与源极区域隔开的第一导电类型的漏极区域和在阻挡层与源极区域和漏极区域之间的第二导电类型的浮动体。 浮体包括在源极区域和漏极区域之间的凹陷区域。 还提供了形成单晶体管浮体动态随机存取存储器（DRAM）单元的方法。

    DRAM device and method of manufacturing the same
    8.
    发明授权
    DRAM device and method of manufacturing the same 失效
    DRAM装置及其制造方法

    公开(公告)号：US07384841B2

    公开(公告)日：2008-06-10

    申请号：US11358060

    申请日：2006-02-22

    申请人： Hong-Sik Yoon ,  In-Seok Yeo ,  Seung-Jae Baik ,  Zong-Liang Huo ,  Shi-Eun Kim

    发明人： Hong-Sik Yoon ,  In-Seok Yeo ,  Seung-Jae Baik ,  Zong-Liang Huo ,  Shi-Eun Kim

    IPC分类号： H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L27/10873 ,  H01L27/10829

    摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

    摘要翻译： 在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。 非导电图案具有比导电图案的带隙大的带隙。 在MTJ结构的侧壁上形成栅极绝缘层和栅电极。 字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。 电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因​​此DRAM器件需要较小的衬底表面积。

    Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure
    9.
    发明授权
    Methods of fabricating a single transistor floating body DRAM cell having recess channel transistor structure 失效
    制造具有凹槽沟道晶体管结构的单晶体管浮体DRAM单元的方法

    公开(公告)号：US07338862B2

    公开(公告)日：2008-03-04

    申请号：US11335333

    申请日：2006-01-19

    申请人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    发明人： Zong-Liang Huo ,  Seung-Jae Baik ,  In-Seok Yeo ,  Hong-Sik Yoon ,  Shi-Eun Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/7841 ,  H01L29/78648

    摘要： Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region within the body layer. A recess region is formed in the floating body region. A gate electrode is formed in the recess region. Impurity ions of a first conductivity type are implanted into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.

    摘要翻译： 制造单晶体管浮体动态随机存取存储器（DRAM）单元的方法包括在半导体衬底上形成阻挡层。 主体层形成在阻挡层上。 形成隔离层，限定体层内的浮体区域。 在浮体区域中形成有凹部。 在凹陷区域中形成栅电极。 第一导电类型的杂质离子注入到凹陷区域的第一侧上的浮体区域的一部分中，以限定源极区域并且在凹陷区域的相对侧上限定浮体的一部分以限定漏极 区域提供浮体。

    DRAM device and method of manufacturing the same
    10.
    发明申请
    DRAM device and method of manufacturing the same 失效
    DRAM装置及其制造方法

    公开(公告)号：US20060197131A1

    公开(公告)日：2006-09-07

    申请号：US11358060

    申请日：2006-02-22

    申请人： Hong-Sik Yoon ,  In-Seok Yeo ,  Seung-Jae Baik ,  Zong-Liang Huo ,  Shi-Eun Kim

    发明人： Hong-Sik Yoon ,  In-Seok Yeo ,  Seung-Jae Baik ,  Zong-Liang Huo ,  Shi-Eun Kim

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10873 ,  H01L27/10829

    摘要： In a DRAM device and a method of manufacturing the same, a multiple tunnel junction (MTJ) structure is provided, which includes conductive patterns and nonconductive patterns alternately stacked on each other. The nonconductive patterns have a band gap larger than a band gap of the conductive patterns. A gate insulation layer and a gate electrode are formed on a sidewall of the MTJ structure. A word line is connected with the MTJ structure, and a bit line is connected with one of top and bottom surfaces of the MTJ structure. A capacitor is connected with one of top and bottom surfaces of the MTJ structure that is not connected with the bit line. Current leakage in the DRAM device is reduced and a unit cells may be vertically stacked on the substrate, so a smaller surface area of the substrate is required for the DRAM device.

    摘要翻译： 在DRAM器件及其制造方法中，提供了多隧道结（MTJ）结构，其包括彼此交替堆叠的导电图案和非导电图案。 非导电图案具有比导电图案的带隙大的带隙。 在MTJ结构的侧壁上形成栅极绝缘层和栅电极。 字线与MTJ结构连接，位线与MTJ结构的顶面和底面之一连接。 电容器与MTJ结构的一个顶表面和底表面连接，不与位线连接。 DRAM器件中的电流泄漏减少，并且单元电池可以垂直地堆叠在衬底上，因​​此DRAM器件需要较小的衬底表面积。